公开(公告)号：US20080213943A1

公开(公告)日：2008-09-04

申请号：US12040775

申请日：2008-02-29

Applicant: Naohide Takamoto ,  Sadahito Misumi ,  Takeshi Matsumura ,  Yasuhiro Amano ,  Masami Oikawa ,  Tsubasa Miki

Inventor： Naohide Takamoto ,  Sadahito Misumi ,  Takeshi Matsumura ,  Yasuhiro Amano ,  Masami Oikawa ,  Tsubasa Miki

IPC: H01L21/58 ,  H01B1/12

CPC classification number: H01L24/83 ,  H01L21/6836 ,  H01L23/3121 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L25/0657 ,  H01L2221/68327 ,  H01L2224/05599 ,  H01L2224/274 ,  H01L2224/2919 ,  H01L2224/29198 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2224/83855 ,  H01L2224/83885 ,  H01L2224/85001 ,  H01L2224/85099 ,  H01L2224/85205 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/20102 ,  H01L2924/20103 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/0635 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012

Abstract: The thermosetting die bonding film of the invention is a thermosetting die bonding film used to produce a semiconductor device, which contains, as main components, 5 to 15% by weight of a thermoplastic resin component and 45 to 55% by weight of a thermosetting resin component, and has a melt viscosity of 400 Pa·s or more and 2500 Pa·s or less at 100° C. before the film is thermally set.

Abstract translation: 本发明的热固性芯片接合薄膜是用于制造半导体器件的热固性芯片接合薄膜，其以主要成分为5〜15重量％的热塑性树脂成分和45〜55重量％的热硬化性树脂 并且在热固化膜之前，在100℃下具有400Pa.s以上且2500Pa·s以下的熔融粘度。

公开(公告)号：US08524007B2

公开(公告)日：2013-09-03

申请号：US12977762

申请日：2010-12-23

Applicant: Daisuke Uenda ,  Yukio Arimitsu ,  Yoshio Terada ,  Yasuhiro Amano ,  Akihisa Murata

Inventor： Daisuke Uenda ,  Yukio Arimitsu ,  Yoshio Terada ,  Yasuhiro Amano ,  Akihisa Murata

IPC: B08B7/00 ,  B32B3/30 ,  B32B17/10

CPC classification number: B08B1/00 ,  B08B7/0028 ,  H01L21/02096 ,  Y10T428/24355 ,  Y10T428/2457 ,  Y10T428/24612 ,  Y10T428/31

Abstract: A cleaning sheet including a cleaning layer which has a microasperity shape having an arithmetic average roughness Ra of 0.05 μm or less and a maximum height Rz of 1.0 μm or less. Preferably, a substantial surface area of the cleaning layer per a flat surface of 1 mm2 is 150% or more of a substantial surface area of a silicon wafer mirror surface per a flat area of 1 mm2. The cleaning sheet may be provided on at least one surface of a transfer member so that the transfer member has a cleaning function. When the cleaning sheet or the transfer member having a cleaning function is transferred in a substrate processing apparatus in place of a substrate to be processed therein, the cleaning sheet contacts and cleans a site of the substrate processing apparatus.

Abstract translation: 一种清洁片，包括具有0.05微米以下的算术平均粗糙度Ra和1.0mum以下的最大高度Rz的微细度形状的清洁层。 优选地，每1mm平坦表面的清洁层的基本表面积为1mm 2的平坦区域的硅晶片镜表面的基本表面积的150％或更多。 清洁片可以设置在转印构件的至少一个表面上，使得转印构件具有清洁功能。 当清洁片或具有清洁功能的转印元件在衬底处理设备中转移以代替待处理衬底时，清洁片接触并清洁衬底处理设备的位置。

公开(公告)号：US20120058625A1

公开(公告)日：2012-03-08

申请号：US13224554

申请日：2011-09-02

Applicant: Yasuhiro AMANO ,  Miki MORITA

Inventor： Yasuhiro AMANO ,  Miki MORITA

IPC: B32B3/02 ,  B32B27/00 ,  H01L21/78 ,  B32B9/04

CPC classification number: H01L21/67132 ,  H01L21/67092 ,  Y10T428/21 ,  Y10T428/31504 ,  Y10T428/31855

Abstract: The present invention provides a film for a semiconductor device that is capable of suppressing the generation of a transfer mark on an adhesive film when a film for a semiconductor device, in which an adhesive film with a dicing sheet obtained by laminating an adhesive film onto a dicing film is laminated onto a cover film leaving a prescribed spacing, is wound up into a roll. It is a film for a semiconductor device in which an adhesive film with a dicing sheet obtained by laminating an adhesive film onto a dicing film is laminated onto a cover film leaving a prescribed spacing, wherein a ratio Ea/Eb of the tensile storage modulus Ea of the adhesive film at 23° C. to the tensile storage modulus Eb of the cover film at 23° C. is in a range of 0.001 to 50.

Abstract translation: 本发明提供了一种半导体装置用薄膜，其能够抑制在将半导体装置的膜用粘合膜层压到 将切割膜层压到留有规定间隔的覆盖膜上，卷绕成卷。 作为半导体装置的膜，其中将具有通过将粘合剂膜层压到切割膜上而获得的切割片的粘合剂膜层压到具有规定间隔的覆盖膜上，其中拉伸储能模量Ea的比Ea / Eb 的粘合膜在23℃下的覆盖膜的拉伸储能模量Eb在0.001〜50的范围内。

公开(公告)号：US07793668B2

公开(公告)日：2010-09-14

申请号：US11014779

申请日：2004-12-20

Applicant: Makoto Namikawa ,  Yoshio Terada ,  Jirou Nukaga ,  Eiji Toyoda ,  Hirofumi Fujii ,  Daisuke Uenda ,  Asami Funatsu ,  Nobuaki Maruoka ,  Hitoshi Ishizaka ,  Yasuhiro Amano

Inventor： Makoto Namikawa ,  Yoshio Terada ,  Jirou Nukaga ,  Eiji Toyoda ,  Hirofumi Fujii ,  Daisuke Uenda ,  Asami Funatsu ,  Nobuaki Maruoka ,  Hitoshi Ishizaka ,  Yasuhiro Amano

IPC: B08B3/00

CPC classification number: B08B1/00 ,  B08B7/00 ,  B08B7/0028 ,  Y10T428/2848 ,  Y10T428/31721

Abstract: A cleaning sheet for cleaning foreign matters away from the interior of the substrate processing equipment is provided. The cleaning sheet includes a cleaning layer having substantially no tackiness and having a tensile modulus of not lower than 0.98 N/mm2 as determined according to JIS K7127. Alternatively, the cleaning sheet includes a cleaning layer having a Vickers hardness of not lower than 10 MPa.

Abstract translation: 提供了一种用于清除离开基板处理设备内部的异物的清洁片。 清洁片包括基本上没有粘性并且根据JIS K7127测定的拉伸模量不低于0.98N / mm 2的清洁层。 或者，清洁片包括维氏硬度不低于10MPa的清洁层。

公开(公告)号：US20100093154A1

公开(公告)日：2010-04-15

申请号：US12529070

申请日：2008-01-28

Applicant: Yasuhiro Amano ,  Sadahito Misumi ,  Takeshi Matsumura

Inventor： Yasuhiro Amano ,  Sadahito Misumi ,  Takeshi Matsumura

IPC: H01L21/301 ,  B32B7/10 ,  H01L21/52 ,  H01L21/683

CPC classification number: H01L23/3121 ,  C08G18/4045 ,  C08G18/6254 ,  C08L33/08 ,  C09J175/04 ,  H01L21/6836 ,  H01L24/27 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68327 ,  H01L2224/274 ,  H01L2224/27436 ,  H01L2224/29 ,  H01L2224/29101 ,  H01L2224/2919 ,  H01L2224/29198 ,  H01L2224/2929 ,  H01L2224/29311 ,  H01L2224/29316 ,  H01L2224/29318 ,  H01L2224/29324 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/29371 ,  H01L2224/29386 ,  H01L2224/29393 ,  H01L2224/32014 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83191 ,  H01L2224/83855 ,  H01L2224/8388 ,  H01L2224/83885 ,  H01L2224/85201 ,  H01L2224/85205 ,  H01L2224/92247 ,  H01L2225/0651 ,  H01L2225/06572 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01016 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/15747 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10T428/24355 ,  H01L2924/00014 ,  H01L2924/0635 ,  H01L2924/066 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2924/05442 ,  H01L2924/05432 ,  H01L2924/0532 ,  H01L2924/04642 ,  H01L2924/05042 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299

Abstract: A dicing die-bonding film in which the adhesive properties during the dicing step and the peeling properties during the pickup step are controlled so that both become good, and a production method thereof, are provided. The dicing die-bonding film in the present invention is a dicing die-bonding film having a pressure-sensitive adhesive layer on a base material and a die bond layer on the pressure-sensitive adhesive layer, in which the arithmetic mean roughness X (μm) on the pressure-sensitive adhesive layer side in the die bond layer is 0.015 μm to 1 μm, the arithmetic mean roughness Y (μm) on the die bond layer side in the pressure-sensitive adhesive layer is 0.03 μm to 1 μm, and the absolute value of the difference of the X and Y is 0.015 or more.

Abstract translation: 控制在切割步骤期间的粘合性能和拾取步骤期间的剥离性能使其都变得良好的切割芯片接合薄膜及其制备方法。 本发明的切割/芯片接合薄膜是在基材上具有压敏粘合剂层和压敏粘合剂层上的芯片接合层的切割芯片接合薄膜，其中算术平均粗糙度X（μm ）为0.015μm〜1μm，压敏粘合剂层的芯片接合层侧的算术平均粗糙度Y（μm）为0.03μm〜1μm， X和Y的差的绝对值为0.015以上。

公开(公告)号：US06437631B2

公开(公告)日：2002-08-20

申请号：US09867354

申请日：2001-05-29

Applicant: Yasuhiro Amano

Inventor： Yasuhiro Amano

IPC: G06F744

CPC classification number: G06G7/163

Abstract: A first analog differential signal V1p and a first analog differential signal V1n are applied to the respectively commonly-connected bases of two sets of differential pairs which are constructed of transistors Q1 to Q4. A commonly-connected collector of Q1 and Q4 is used as an output terminal Vop, whereas a commonly-connected collector of Q2 and Q3 is used as another output terminal Von. Collectors of Q11 and Q12 are connected to the respective commonly-connected emitters of these differential pairs. Parallel resonant circuits are connected to the respective emitters of Q11 and Q12, and the emitter-to-emitter path is connected by R15. Input circuits 101 and 102 are connected to the respective bases of Q11 and Q12. A second analog differential signal V2p and a second analog differential signal V2n are inputted to these input circuits 101 and 102. The transistors Q12 and Q14 of the input circuits 101 and 102 constitute current mirror circuits in connection with Q11 and Q13. A total number of longitudinally-stacked stages of the transistors can be made of two stages, and also the analog multiplying circuit can be operated under low power supply voltage.

Abstract translation: 第一模拟差分信号V1p和第一模拟差分信号V1n被施加到由晶体管Q1至Q4构成的两组差分对的各自共同连接的基极。 Q1和Q4的共同连接的集电极用作输出端子Vop，而Q2和Q3的共同连接的集电极用作另一个输出端子Von。 Q11和Q12的集电极连接到这些差分对的各个共同连接的发射极。 并联谐振电路连接到Q11和Q12的各个发射极，发射极到发射极的路径由R15连接。 输入电路101和102连接到Q11和Q12的各个基极。 第二模拟差分信号V2p和第二模拟差分信号V2n输入到这些输入电路101和102.输入电路101和102的晶体管Q12和Q14构成与Q11和Q13有关的电流镜电路。 晶体管的纵向堆叠级的总数可以由两级制成，并且模拟乘法电路也可以在低电源电压下操作。