FILM FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    4.
    发明申请
    FILM FOR MANUFACTURING SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
    制造半导体器件的薄膜及其制造方法

    公开(公告)号:US20100136275A1

    公开(公告)日:2010-06-03

    申请号:US12629296

    申请日:2009-12-02

    Applicant: Yasuhiro Amano

    Inventor: Yasuhiro Amano

    Abstract: A present invention relates to a film for manufacturing a semiconductor device in which a cover film is pasted onto a laminated film, wherein the shrinkage in the longitudinal direction and in the lateral direction in the laminated film after peeling the cover film and leaving for 24 hours at a temperature of 23±2° C. is in a range of 0 to 2% compared to the laminated film before pasting of the cover film.

    Abstract translation: 本发明涉及一种用于制造半导体器件的膜,其中将覆盖膜粘贴到层压膜上,其中在剥离覆盖膜之后层压膜中的纵向和横向上的收缩并且留置24小时 与贴膜前的层叠膜相比,在23±2℃的温度下为0〜2%的范围。

    Cleaning sheet, transfer member provided with cleaning function, and method for cleaning substrate processing apparatus
    7.
    发明授权
    Cleaning sheet, transfer member provided with cleaning function, and method for cleaning substrate processing apparatus 失效
    具有清洁功能的清洁片,转印部件以及清洗基板处理装置的方法

    公开(公告)号:US08524007B2

    公开(公告)日:2013-09-03

    申请号:US12977762

    申请日:2010-12-23

    Abstract: A cleaning sheet including a cleaning layer which has a microasperity shape having an arithmetic average roughness Ra of 0.05 μm or less and a maximum height Rz of 1.0 μm or less. Preferably, a substantial surface area of the cleaning layer per a flat surface of 1 mm2 is 150% or more of a substantial surface area of a silicon wafer mirror surface per a flat area of 1 mm2. The cleaning sheet may be provided on at least one surface of a transfer member so that the transfer member has a cleaning function. When the cleaning sheet or the transfer member having a cleaning function is transferred in a substrate processing apparatus in place of a substrate to be processed therein, the cleaning sheet contacts and cleans a site of the substrate processing apparatus.

    Abstract translation: 一种清洁片,包括具有0.05微米以下的算术平均粗糙度Ra和1.0mum以下的最大高度Rz的微细度形状的清洁层。 优选地,每1mm平坦表面的清洁层的基本表面积为1mm 2的平坦区域的硅晶片镜表面的基本表面积的150%或更多。 清洁片可以设置在转印构件的至少一个表面上,使得转印构件具有清洁功能。 当清洁片或具有清洁功能的转印元件在衬底处理设备中转移以代替待处理衬底时,清洁片接触并清洁衬底处理设备的位置。

    Analog multiplying circuit and variable gain amplifying circuit
    10.
    发明授权
    Analog multiplying circuit and variable gain amplifying circuit 有权
    模拟乘法电路和可变增益放大电路

    公开(公告)号:US06437631B2

    公开(公告)日:2002-08-20

    申请号:US09867354

    申请日:2001-05-29

    Applicant: Yasuhiro Amano

    Inventor: Yasuhiro Amano

    CPC classification number: G06G7/163

    Abstract: A first analog differential signal V1p and a first analog differential signal V1n are applied to the respectively commonly-connected bases of two sets of differential pairs which are constructed of transistors Q1 to Q4. A commonly-connected collector of Q1 and Q4 is used as an output terminal Vop, whereas a commonly-connected collector of Q2 and Q3 is used as another output terminal Von. Collectors of Q11 and Q12 are connected to the respective commonly-connected emitters of these differential pairs. Parallel resonant circuits are connected to the respective emitters of Q11 and Q12, and the emitter-to-emitter path is connected by R15. Input circuits 101 and 102 are connected to the respective bases of Q11 and Q12. A second analog differential signal V2p and a second analog differential signal V2n are inputted to these input circuits 101 and 102. The transistors Q12 and Q14 of the input circuits 101 and 102 constitute current mirror circuits in connection with Q11 and Q13. A total number of longitudinally-stacked stages of the transistors can be made of two stages, and also the analog multiplying circuit can be operated under low power supply voltage.

    Abstract translation: 第一模拟差分信号V1p和第一模拟差分信号V1n被施加到由晶体管Q1至Q4构成的两组差分对的各自共同连接的基极。 Q1和Q4的共同连接的集电极用作输出端子Vop,而Q2和Q3的共同连接的集电极用作另一个输出端子Von。 Q11和Q12的集电极连接到这些差分对的各个共同连接的发射极。 并联谐振电路连接到Q11和Q12的各个发射极,发射极到发射极的路径由R15连接。 输入电路101和102连接到Q11和Q12的各个基极。 第二模拟差分信号V2p和第二模拟差分信号V2n输入到这些输入电路101和102.输入电路101和102的晶体管Q12和Q14构成与Q11和Q13有关的电流镜电路。 晶体管的纵向堆叠级的总数可以由两级制成,并且模拟乘法电路也可以在低电源电压下操作。

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