公开(公告)号：US08334196B2

公开(公告)日：2012-12-18

申请号：US12917339

申请日：2010-11-01

Applicant: Ying-Cheng Chuang ,  Hung-Ming Tsai ,  Sheng-Wei Yang ,  Ping-Cheng Hsu ,  Ming-Cheng Chang

Inventor： Ying-Cheng Chuang ,  Hung-Ming Tsai ,  Sheng-Wei Yang ,  Ping-Cheng Hsu ,  Ming-Cheng Chang

IPC: H01L21/768 ,  H01L21/28

CPC classification number: H01L27/10876 ,  H01L21/28531 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888

Abstract: A method of forming a conductive contact includes forming a structure comprising an upper surface joining with a sidewall surface. The sidewall surface contains elemental-form silicon. Silicon is epitaxially grown from the sidewall surface. Dielectric material is formed over the upper surface and the epitaxially-grown silicon. A conductive contact is formed through the dielectric material to conductively connect with the upper surface.

Abstract translation: 形成导电接触的方法包括形成包括与侧壁表面接合的上表面的结构。 侧壁表面含有元素型硅。 硅从侧壁表面外延生长。 电介质材料形成在上表面和外延生长的硅上。 通过电介质材料形成导电接触，以与上表面导电连接。

公开(公告)号：US20120119277A1

公开(公告)日：2012-05-17

申请号：US12945536

申请日：2010-11-12

Applicant: YING CHENG CHUANG ,  PING CHENG HSU ,  SHENG WEI YANG ,  MING CHENG CHANG ,  HUNG MING TSAI

Inventor： YING CHENG CHUANG ,  PING CHENG HSU ,  SHENG WEI YANG ,  MING CHENG CHANG ,  HUNG MING TSAI

IPC: H01L27/108 ,  H01L27/088 ,  H01L21/8242

CPC classification number: H01L21/76224 ,  H01L27/10876 ,  H01L27/10891

Abstract: A memory device includes a plurality of isolations and trench fillers arranged in an alternating manner in a direction, a plurality of mesa structures between the isolations and trench fillers, and a plurality of word lines each overlying a side surface of the respective mesa. In one embodiment of the present invention, the width measured in the direction of the trench filler is smaller than that of the isolation, each mesa structure includes at least one paired source/drain regions and at least one channel base region corresponding to the paired source/drain regions, and each of the word lines is on a side surface of the mesa structure, adjacent the respective isolation, and is arranged adjacent the channel base region.

Abstract translation: 存储器件包括多个隔离件和沟槽填料，沿方向交替排列，隔离件和沟槽填料之间的多个台面结构，以及各自覆盖相应台面的侧表面的多个字线。 在本发明的一个实施例中，在沟槽填料的方向上测量的宽度小于隔离层的宽度，每个台面结构包括至少一个成对的源极/漏极区域和对应于配对源极的至少一个沟道基极区域 /漏极区域，并且每个字线在台面结构的侧表面上，与相应的隔离相邻，并且被布置为与通道基底区域相邻。

公开(公告)号：US07576381B2

公开(公告)日：2009-08-18

申请号：US11955397

申请日：2007-12-13

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC: H01L27/108

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L29/42336

Abstract: A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.

Abstract translation: 提供了包括基板，第一介电层，第一导电层，第二导电层，第二介电层，间隔物和掺杂区域的存储器结构。 衬底具有沟槽，其中。 第一介电层设置在沟槽的内表面上。 第一导电层设置在沟槽下部的第一电介质层上。 第二导电层设置在第一导电层上方并填充沟槽。 第二电介质层设置在第一导电层和第二导电层之间。 间隔物设置在第一介电层和第二导电层之间。 掺杂区域设置在沟槽侧面的衬底中。

公开(公告)号：US20090014773A1

公开(公告)日：2009-01-15

申请号：US11946868

申请日：2007-11-29

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC: H01L29/78 ,  H01L21/76

CPC classification number: H01L29/7881 ,  H01L29/66825

Abstract: A method for fabricating the memory structure includes: providing a substrate having a pad, forming an opening in the pad, forming a first spacer on a sidewall of the opening, filling the opening with a sacrificial layer, removing the first spacer and exposing a portion of the substrate, removing the exposed substrate to define a first trench and a second trench, removing the sacrificial layer to expose a surface of the substrate to function as a channel region, forming a first dielectric layer on a surface of the first trench, a surface of the second trench and a surface of the channel region, filling the first trench and the second trench with a first conductive layer, forming a second dielectric layer on a surface of the first conductive layer and the surface of the channel region, filling the opening with a second conductive layer, and removing the pad.

Abstract translation: 一种用于制造存储器结构的方法包括：提供具有焊盘的衬底，在焊盘中形成开口，在开口的侧壁上形成第一间隔物，用牺牲层填充开口，移除第一间隔物并露出一部分 去除所述暴露的衬底以限定第一沟槽和第二沟槽，去除所述牺牲层以暴露所述衬底的表面以用作沟道区域，在所述第一沟槽的表面上形成第一介电层， 第二沟槽的表面和沟道区的表面，用第一导电层填充第一沟槽和第二沟槽，在第一导电层的表面和沟道区的表面上形成第二介电层，填充第二沟槽 用第二导电层打开，并移除垫。

公开(公告)号：US20080265302A1

公开(公告)日：2008-10-30

申请号：US11955397

申请日：2007-12-13

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chung-Lin Huang ,  Shih-Yang Chiu

IPC: H01L29/00 ,  H01L21/76

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L29/42336

Abstract: A memory structure including a substrate, a first dielectric layer, a first conducting layer, a second conducting layer, a second dielectric layer, a spacer and a doped region is provided. The substrate has a trench wherein. The first dielectric layer is disposed on the interior surface of the trench. The first conducting layer is disposed on the first dielectric layer of the lower portion of the trench. The second conducting layer is disposed above the first conducting layer and filling the trench. The second dielectric layer is disposed between the first conducting layer and the second conducting layer. The spacer is disposed between the first dielectric layer and the second conducting layer. The doped region is disposed in the substrate of a side of the trench.

Abstract translation: 提供了包括基板，第一介电层，第一导电层，第二导电层，第二介电层，间隔物和掺杂区域的存储器结构。 衬底具有沟槽，其中。 第一介电层设置在沟槽的内表面上。 第一导电层设置在沟槽下部的第一电介质层上。 第二导电层设置在第一导电层上方并填充沟槽。 第二电介质层设置在第一导电层和第二导电层之间。 间隔物设置在第一介电层和第二导电层之间。 掺杂区域设置在沟槽侧面的衬底中。

公开(公告)号：US07323743B2

公开(公告)日：2008-01-29

申请号：US11603771

申请日：2006-11-22

Applicant: Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

Inventor： Ying-Cheng Chuang ,  Chung-Lin Huang ,  Chi-Hui Lin

IPC: H01L29/788

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7881

Abstract: A floating gate and fabrication method thereof. A semiconductor substrate is provided, on which an oxide layer, a first conducting layer, and a patterned hard mask layer having an opening are sequentially formed. A spacer is formed on the sidewall of the opening. A second conducting layer is formed on the hard mask layer. The second conducting layer is planarized to expose the surface of the patterned hard mask layer. The surface of the second conducting layer is oxidized to form an oxide layer. The patterned hard mask layer and the oxide layer and the first conducting layer underlying the patterned hard mask layer are removed.

Abstract translation: 浮栅及其制造方法。 提供了半导体衬底，其上依次形成有氧化物层，第一导电层和具有开口的图案化硬掩模层。 间隔件形成在开口的侧壁上。 在硬掩模层上形成第二导电层。 将第二导电层平坦化以暴露图案化硬掩模层的表面。 第二导电层的表面被氧化形成氧化物层。 图案化的硬掩模层和氧化物层以及图案化的硬掩模层下面的第一导电层被去除。

公开(公告)号：US07135731B2

公开(公告)日：2006-11-14

申请号：US10707396

申请日：2003-12-10

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang ,  Chi-Hui Lin

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC classification number: H01L27/10876 ,  H01L27/10841 ,  H01L27/10864 ,  H01L27/10885 ,  Y10S257/905 ,  Y10S257/906 ,  Y10S257/908

Abstract: A vertical DRAM and fabrication method thereof. The vertical DRAM has a plurality of memory cells on a substrate, and each of the memory cells has a trench capacitor, a vertical transistor, and a source-isolation oxide layer in a deep trench. The main advantage of the present invention is to form an annular source diffusion and an annular drain diffusion of the vertical transistor around the sidewall of the deep trench. As a result, when a gate of the transistor is turned on, an annular gate channel is provided. The width of the gate channel of the present invention is therefore increased.

Abstract translation: 垂直DRAM及其制造方法。 垂直DRAM在衬底上具有多个存储单元，并且每个存储单元在深沟槽中具有沟槽电容器，垂直晶体管和源极隔离氧化物层。 本发明的主要优点是在深沟槽的侧壁周围形成环形源极扩散和垂直晶体管的环形漏极扩散。 结果，当晶体管的栅极导通时，提供环形栅极沟道。 因此，本发明的栅极通道的宽度增加。

公开(公告)号：US07115477B2

公开(公告)日：2006-10-03

申请号：US10884769

申请日：2004-07-02

Applicant: Chung-Lin Huang ,  Ying-Cheng Chuang

Inventor： Chung-Lin Huang ,  Ying-Cheng Chuang

IPC: H01L21/336

CPC classification number: H01L29/512 ,  H01L21/26506 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/2822 ,  H01L29/4983 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66583

Abstract: A gate with dual gate dielectric layer and fabrication method thereof. A semiconductor substrate is provided, on which a dielectric layer and a patterned hard mask layer with an opening are sequentially formed. A spacer is formed on a sidewall of the opening. The semiconductor substrate is ion implanted, the spacer and the exposed dielectric layer are removed, and a gate oxide layer is formed on the bottom of the opening.

Abstract translation: 具有双栅介质层的栅极及其制造方法。 提供半导体衬底，其上依次形成介电层和具有开口的图案化硬掩模层。 间隔件形成在开口的侧壁上。 离子注入半导体衬底，去除间隔物和暴露的电介质层，并且在开口的底部形成栅极氧化物层。

公开(公告)号：US20060088967A1

公开(公告)日：2006-04-27

申请号：US11114735

申请日：2005-04-26

Applicant: Ching-Nan Hsiao ,  Ying-Cheng Chuang

Inventor： Ching-Nan Hsiao ,  Ying-Cheng Chuang

IPC: H01L21/336

CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

Abstract: The present invention provides a method of manufacturing a FinFET transistor, comprising the steps of: forming a plurality of trenches in a semiconductor substrate, forming a dielectric layer on the semiconductor substrate and filling the trenches, and etching back the dielectric layer to a level below the surface of the substrate to form one or more semiconductor fins standing between the trenches as an active region, such as a source, drain, and channel for the FinFET transistor.

Abstract translation: 本发明提供一种制造FinFET晶体管的方法，包括以下步骤：在半导体衬底中形成多个沟槽，在半导体衬底上形成电介质层并填充沟槽，并将电介质层回蚀刻到低于 衬底的表面以形成一个或多个位于沟槽之间的半导体鳍片作为有源区域，例如用于FinFET晶体管的源极，漏极和沟道。

公开(公告)号：US07005701B2

公开(公告)日：2006-02-28

申请号：US10318551

申请日：2002-12-13

Applicant: Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

Inventor： Ching-Nan Hsiao ,  Chi-Hui Lin ,  Chung-Lin Huang ,  Ying-Cheng Chuang

IPC: H01L29/76 ,  H01L39/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC classification number: H01L27/11568 ,  H01L27/115

Abstract: A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.

Abstract translation: 一种用于制造垂直氮化物只读存储器（NROM）单元的方法。 提供具有至少一个沟槽的衬底。 间隔件形成在沟槽的侧壁上。 随后，使用间隔物作为掩模在衬底上进行离子注入，以在沟槽的表面和底部附近的衬底中形成作为位线的掺杂区域。 在每个掺杂区域上形成位线氧化物。 在移除间隔物之后，在沟槽的侧壁和位线氧化物的表面上沉积作为栅极电介质的适形绝缘层。 最后，作为字线的导电层沉积在绝缘层上并填充在沟槽中。