-
公开(公告)号：US11728313B2
公开(公告)日：2023-08-15
申请号：US17246845
申请日：2021-05-03
发明人： Bongsub Lee , Guilian Gao
IPC分类号： H01L25/065 , H01L23/00 , H01L23/48 , H01L23/482 , H01L21/768 , H01L23/522
CPC分类号： H01L25/0657 , H01L21/76843 , H01L21/76895 , H01L23/481 , H01L23/4824 , H01L23/5226 , H01L24/09 , H01L24/32 , H01L24/80 , H01L24/83 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2225/06524 , H01L2225/06544
摘要： Representative techniques and devices including process steps may be employed to mitigate the potential for delamination of bonded microelectronic substrates due to metal expansion at a bonding interface. For example, a metal pad may be disposed at a bonding surface of at least one of the microelectronic substrates, where the contact pad is positioned offset relative to a TSV in the substrate and electrically coupled to the TSV.
-
公开(公告)号：US20230215836A1
公开(公告)日：2023-07-06
申请号：US18145607
申请日：2022-12-22
发明人： Belgacem Haba , Rajesh Katkar , Guilian Gao , Cyprian Emeka Uzoh
IPC分类号： H01L23/00
CPC分类号： H01L24/80 , H01L24/08 , H01L2224/08225 , H01L2224/80006 , H01L2224/80895 , H01L2224/80896
摘要： A bonded structure with a package substrate comprising an inorganic, insulating first bonding layer and first conductive features at a surface thereof and an electronic component comprising an inorganic, insulating second bonding layer and second conductive features at a surface thereof wherein the first bonding layer and the second bonding layer are directly bonded to one another, and the first and second conductive features are directly bonded to one another.
-
公开(公告)号：US20230197655A1
公开(公告)日：2023-06-22
申请号：US18068150
申请日：2022-12-19
IPC分类号： H01L23/00
CPC分类号： H01L24/08 , H01L24/05 , H01L2224/08145 , H01L2224/05583 , H01L2224/05582 , H01L2224/05647 , H01L2224/05686 , H01L2924/04941 , H01L2924/04953 , H01L2224/05681 , H01L2224/05693 , H01L2924/05432 , H01L2924/05042 , H01L2924/04642
摘要： Methods for fabrication dielectric layers having conductive contact pads, and directly bonding the dielectric and conductive bonding surfaces of the dielectric layers. In some aspects, the method includes disposing a polish stop layer on dielectric bonding surfaces on top of a dielectric layer. A conductive layer is disposed on top of the polish stop layer and then polished to form conductive contact pads having polished conducting bonding surfaces. During the polishing process, the polish stop layer reduces rounding of dielectric edges and erosion of the dielectric bonding surfaces between closely spaced conductive bonding surfaces. The resulting polished dielectric and conductive bonding surfaces are directly bonded to dielectric and conductive bonding surfaces of another dielectric layer to form conductive interconnects.
-
公开(公告)号：US20230187412A1
公开(公告)日：2023-06-15
申请号：US18048586
申请日：2022-10-21
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00
CPC分类号： H01L25/0657 , H01L24/08 , H01L24/48 , H01L25/50 , H01L25/18
摘要： A stacked electronic device is disclosed. The stacked electronic device can comprise a die stack including two or more connected dies, such as a lower die, an upper die, and a middle die between the lower die and the upper die. A plurality of through substrate vias (TSVs) can provide signal transmission to dies of the stack. A power supply path can be configured to provide power to the middle die without passing through the lower die. In some embodiments, external paths can provide power through an upper surface of a die in the stack while signals are supplied through the lower surface.
-
25.发明申请公开(公告)号：US20230118156A1
公开(公告)日：2023-04-20
申请号：US18069485
申请日：2022-12-21
发明人： Guilian Gao , Gaius Gillman Fountain, JR. , Laura Wills Mirkarimi , Rajesh Katkar , Ilyas Mohammed , Cyprian Emeka Uzoh
IPC分类号： H01L23/00 , H01L23/522 , H01L21/768
摘要： Layer structures for making direct metal-to-metal bonds at low temperatures and shorter annealing durations in microelectronics are provided. Example bonding interface structures enable direct metal-to-metal bonding of interconnects at low annealing temperatures of 150° C. or below, and at a lower energy budget. The example structures provide a precise metal recess distance for conductive pads and vias being bonded that can be achieved in high volume manufacturing. The example structures provide a vertical stack of conductive layers under the bonding interface, with geometries and thermal expansion features designed to vertically expand the stack at lower temperatures over the precise recess distance to make the direct metal-to-metal bonds. Further enhancements, such as surface nanotexture and copper crystal plane selection, can further actuate the direct metal-to-metal bonding at lowered annealing temperatures and shorter annealing durations.
-
公开(公告)号：US11515279B2
公开(公告)日：2022-11-29
申请号：US16995988
申请日：2020-08-18
发明人： Cyprian Emeka Uzoh , Jeremy Alfred Theil , Liang Wang , Rajesh Katkar , Guilian Gao , Laura Wills Mirkarimi
IPC分类号： H01L23/00
摘要： Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
-
公开(公告)号：US12068278B2
公开(公告)日：2024-08-20
申请号：US18148369
申请日：2022-12-29
IPC分类号： H01L23/00 , H01L21/02 , H01L21/3065 , H01L21/308 , H01L21/311 , H01L21/683 , H01L21/78 , H01L23/31 , H01L25/00 , H01L25/065
CPC分类号： H01L24/83 , H01L21/02076 , H01L21/3085 , H01L21/31116 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L23/3185 , H01L25/0657 , H01L25/50 , H01L21/3065 , H01L2221/68327 , H01L2221/68354 , H01L2221/68368 , H01L2224/83013 , H01L2224/83031 , H01L2224/83895 , H01L2224/83896
摘要： Representative implementations of techniques and methods include processing singulated dies in preparation for bonding. A plurality of semiconductor die components may be singulated from a wafer component, the semiconductor die components each having a substantially planar surface. Particles and shards of material may be removed from edges of the plurality of semiconductor die component. Additionally, one or more of the plurality of semiconductor die components may be bonded to a prepared bonding surface, via the substantially planar surface.
-
公开(公告)号：US12046571B2
公开(公告)日：2024-07-23
申请号：US18058693
申请日：2022-11-23
发明人： Cyprian Emeka Uzoh , Jeremy Alfred Theil , Liang Wang , Rajesh Katkar , Guilian Gao , Laura Wills Mirkarimi
IPC分类号： H01L23/00
CPC分类号： H01L24/26 , H01L24/03 , H01L24/09 , H01L24/27 , H01L24/30 , H01L24/83 , H01L2224/08257 , H01L2924/01025 , H01L2924/01027 , H01L2924/01028
摘要： Devices and techniques including process steps make use of recesses in conductive interconnect structures to form reliable low temperature metallic bonds. A fill layer is deposited into the recesses prior to bonding. First conductive interconnect structures are bonded at ambient temperatures to second metallic interconnect structures using direct bonding techniques, with the fill layers in the recesses in one or both of the first and second interconnect structures.
-
29.发明公开公开(公告)号：US20240213191A1
公开(公告)日：2024-06-27
申请号：US18069910
申请日：2022-12-21
IPC分类号： H01L23/00
CPC分类号： H01L24/05 , H01L24/03 , H01L24/08 , H01L24/80 , H01L2224/03462 , H01L2224/03616 , H01L2224/05147 , H01L2224/08145 , H01L2224/80895 , H01L2224/80896 , H01L2924/3512
摘要： Disclosed is an element including a conductive feature at a contact surface of the element and a nonconductive region at the contact surface in which the conductive feature is at least partially embedded. The contact feature includes a conductive material and an amount of impurities at a grain boundary of the conductive material. The impurities have a non-alloying material that does not form an alloy with the conductive material at a bonding temperature.
-
30.发明公开公开(公告)号：US20240203948A1
公开(公告)日：2024-06-20
申请号：US18589231
申请日：2024-02-27
发明人： Cyprian Emeka Uzoh , Rajesh Katkar , Thomas Workman , Guilian Gao , Gaius Gillman Fountain, JR. , Laura Wills Mirkarimi , Belgacem Haba , Gabriel Z. Guevara , Joy Watanabe
IPC分类号： H01L25/065 , H01L21/56 , H01L23/00 , H01L23/31
CPC分类号： H01L25/0657 , H01L21/561 , H01L23/3121 , H01L24/97 , H01L2224/0401 , H01L2924/3511 , H01L2924/35121
摘要： Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.
-
-
-
-
-
-
-
-
-
搜索结果
47 条记录 (耗时 0.021 秒)
