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    Semiconductor device package and a method of manufacturing the same
    21.
    发明授权
    Semiconductor device package and a method of manufacturing the same 有权

    公开(公告)号：US10381296B2

    公开(公告)日：2019-08-13

    申请号：US15699810

    申请日：2017-09-08

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Li Chuan Tsai ,  Chih-Cheng Lee

    IPC: H01L23/498 ,  H01L21/48 ,  H05K3/34 ,  H05K1/11 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31

    Abstract: At least some embodiments of the present disclosure relate to a substrate for packaging a semiconductor device. The substrate includes a first dielectric layer having a first surface, a first patterned conductive layer adjacent to the first surface of the first dielectric layer, and a conductive post. The first patterned conductive layer includes a first conductive pad and a second conductive pad. The conductive post is disposed on the first conductive pad. The conductive post includes a first portion and a second portion. The first portion and the second portion of the conductive post are exposed by the first dielectric layer. The first portion of the conductive post has a first width corresponding to a top line width of the first portion and the second portion of the conductive post has a width. The width of the second portion of the conductive post is greater than the first width of the first portion of the conductive post.

    Reduced-dimension via-land structure and method of making the same
    22.
    发明授权
    Reduced-dimension via-land structure and method of making the same 有权

    公开(公告)号：US10334728B2

    公开(公告)日：2019-06-25

    申请号：US15019776

    申请日：2016-02-09

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee ,  Po-Shu Peng

    IPC: H05K1/11 ,  H05K3/10 ,  H05K3/40 ,  H05K3/00

    Abstract: A package substrate includes a dielectric layer, a conductive via disposed in the dielectric layer, and a conductive pattern layer exposed from a first surface of the dielectric layer. The conductive pattern layer includes traces and a via land, the via land extends into the conductive via, and a circumferential portion of the via land is encompassed by the conductive via. A method of making a package substrate includes forming a conductive pattern layer including traces and a via land, providing a dielectric layer to cover the conductive pattern layer, and forming a via hole. Forming the via hole is performed by removing a portion of the dielectric layer and exposing a bottom surface of the via land and at least a portion of a side surface of the via land. A conductive material is applied into the via hole to form a conductive via covering the via land.

    Substrate, semiconductor device package and method of manufacturing the same
    27.
    发明授权
    Substrate, semiconductor device package and method of manufacturing the same 有权

    公开(公告)号：US12165963B2

    公开(公告)日：2024-12-10

    申请号：US18375140

    申请日：2023-09-29

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Cheng-Lin Ho ,  Chih-Cheng Lee

    IPC: H01L23/498 ,  H01L21/48 ,  H01L23/31

    Abstract: A substrate includes a first dielectric layer having a first surface and a second dielectric layer having a first surface disposed adjacent to the first surface of the first dielectric layer. The substrate further includes a first conductive via disposed in the first dielectric layer and having a first end adjacent to the first surface of the first dielectric layer and a second end opposite the first end. The substrate further includes a second conductive via disposed in the second dielectric layer and having a first end adjacent to the first surface of the second dielectric layer. A width of the first end of the first conductive via is smaller than a width of the second end of the first conductive via, and a width of the first end of the second conductive via is smaller than the width of the first end of the first conductive via.

    Semiconductor device package and method for manufacturing the same
    30.
    发明授权
    Semiconductor device package and method for manufacturing the same 有权

    公开(公告)号：US11600567B2

    公开(公告)日：2023-03-07

    申请号：US16528352

    申请日：2019-07-31

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Chih-Cheng Lee ,  Kuang Hsiung Chen

    IPC: H01L23/528 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768

    Abstract: A semiconductor device package includes a first circuit layer, a second circuit layer, a first semiconductor die and a second semiconductor die. The first circuit layer includes a first surface and a second surface opposite to the first surface. The second circuit layer is disposed on the first surface of the first circuit layer. The first semiconductor die is disposed on the first circuit layer and the second circuit layer, and electrically connected to the first circuit layer and the second circuit layer. The second semiconductor die is disposed on the second circuit layer, and electrically connected to the second circuit layer.

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