公开(公告)号：US20180358238A1

公开(公告)日：2018-12-13

申请号：US15619415

申请日：2017-06-09

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Jin-Yuan LAI ,  Tang-Yuan CHEN ,  Ying-Xu LU ,  Dao-Long CHEN ,  Kwang-Lung LIN ,  Chih-Pin HUNG ,  Tse-Chuan CHOU ,  Ming-Hung CHEN ,  Chi-Hung PAN

IPC: H01L21/56 ,  H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L21/563 ,  H01L21/481 ,  H01L23/49838 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83143 ,  H01L2224/83493 ,  H01L2224/83888 ,  H01L2224/83889 ,  H01L2924/01006

Abstract: The present disclosure relates to a semiconductor device package comprising a substrate, a semiconductor device, and a underfill. The substrate includes a top surface defining a mounting area, and a barrier section on the top surface and adjacent to the mounting area. The semiconductor device is mounted on the mounting area of the substrate. The underfill is disposed between the semiconductor device and the mounting area and the barrier section of the substrate. A contact angle between a surface of the underfill and the barrier section is greater than or equal to about 90 degrees.

公开(公告)号：US20170278814A1

公开(公告)日：2017-09-28

申请号：US15076831

申请日：2016-03-22

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chih-Pin HUNG ,  Dao-Long CHEN ,  Ying-Ta CHIU ,  Ping-Feng YANG

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/1161 ,  H01L2224/11622 ,  H01L2224/13012 ,  H01L2224/13015 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/81385 ,  H01L2224/81815 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A semiconductor device includes a semiconductor element, a trace disposed adjacent to a surface of the semiconductor element, a bonding pad disposed adjacent to the surface of the semiconductor element and connected to the trace, and a pillar disposed on the bonding pad. The pillar includes a first end wall, a second end wall opposite the first end wall, a first side wall, and a second side wall opposite the first side wall. The first side wall and the second side wall connect the first end wall to the second end wall. One or both of the first side wall and the second side wall incline inwardly from the first end wall to the second end wall. The pillar is disposed on the bonding pad such that the first end wall is closer to the trace than is the second end wall.

公开(公告)号：US20240178158A1

公开(公告)日：2024-05-30

申请号：US18434698

申请日：2024-02-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Po-Hsien KE ,  Teck-Chong LEE ,  Chih-Pin HUNG

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L23/3135 ,  H01L25/0652 ,  H01L25/50

Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device, a second electronic device, a first underfill, a second underfill and a stiff bonding material. The first electronic device and the second electronic device are disposed on the wiring structure, and are electrically connected to each other through the wiring structure. The first underfill is disposed in a first space between the first electronic device and the wiring structure. The second underfill is disposed in a second space between the second electronic device and the wiring structure. The stiff bonding material is disposed in a central gap between the first electronic device and the second electronic device. The stiff bonding material is different from the first underfill and the second underfill.

公开(公告)号：US20240170364A1

公开(公告)日：2024-05-23

申请号：US17993797

申请日：2022-11-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Hung-Hsien HUANG ,  Wen Chun WU ,  Chih-Pin HUNG

IPC: H01L23/427 ,  H01L23/00

CPC classification number: H01L23/427 ,  H01L24/32 ,  H01L23/3736 ,  H01L2224/32245

Abstract: A semiconductor device package and a method of manufacturing a semiconductor device package are provided. The semiconductor device package includes at least one electronic component, a heat source, and a heat dissipation element. The heat source is adjacent to the electronic component. The heat dissipation element is disposed adjacent to the heat source and the electronic component. The heat dissipation element includes a heat transmitting structure configured to reduce heat, which is from the heat source, through the heat dissipation element, and transmitting in a direction toward the electronic component.

公开(公告)号：US20240072413A1

公开(公告)日：2024-02-29

申请号：US17894946

申请日：2022-08-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Cheng-Yu HO ,  Meng-Wei HSIEH ,  Chih-Pin HUNG

IPC: H01Q1/22 ,  H01Q1/52 ,  H01Q21/06 ,  H01Q25/00

CPC classification number: H01Q1/2283 ,  H01Q1/523 ,  H01Q21/065 ,  H01Q25/00

Abstract: An electronic device is provided. The electronic device includes an antenna array including a plurality of antenna patterns collectively configured to provide a scan-angle coverage. Each of the antenna patterns includes a curved surface.

公开(公告)号：US20220310500A1

公开(公告)日：2022-09-29

申请号：US17213006

申请日：2021-03-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun CHANG ,  Chih-Pin HUNG ,  Teck-Chong LEE ,  Chih-Yi HUANG

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/544 ,  H01L25/065 ,  H01L21/48

Abstract: An assembly structure and a method for manufacturing an assembly structure are provided. The assembly structure includes a wiring structure and a semiconductor element. The wiring structure includes at least one dielectric layer and at least one circuit layer in contact with the at least one dielectric layer, and defines an accommodating recess recessed from a top surface of the wiring structure. The wiring structure has a smooth surface extending from the top surface of the wiring structure to a surface of the accommodating recess. The semiconductor element is disposed in the accommodating recess.

公开(公告)号：US20210288024A1

公开(公告)日：2021-09-16

申请号：US17322764

申请日：2021-05-17

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan CHEN ,  Meng-Kai SHIH ,  Teck-Chong LEE ,  Shin-Luh TARNG ,  Chih-Pin HUNG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/528 ,  H01L21/56

Abstract: A semiconductor device package includes a first conductive layer, a second conductive layer and a third conductive layer. The first conductive layer has a first pitch. The second conductive layer has a second pitch and is arranged at two different sides of the first conductive layer. The third conductive layer has a third pitch and is disposed above the first conductive layer and the second conductive layer. The third conductive layer is electrically connected to the first conductive layer. The first pitch is smaller than the third pitch, and the third pitch is smaller than the second pitch.

公开(公告)号：US20200381338A1

公开(公告)日：2020-12-03

申请号：US16430260

申请日：2019-06-03

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tang-Yuan CHEN ,  Yuan Tzuo LUO ,  Shao-Cheng YEN ,  Meng-Kai SHIH ,  Chih-Pin HUNG

IPC: H01L23/433 ,  H01L23/31 ,  H01L21/56

Abstract: A semiconductor device package includes a carrier, an electronic component, a package body and a ring structure. The electronic component is disposed on the carrier. The electronic component has a side surface. The package body is disposed on the carrier. The package body exposes at least a portion of the side surface of the electronic component. The ring structure is disposed on the package body and surrounds the portion of the side surface of the electronic component exposed from the package body.

公开(公告)号：US20190341368A1

公开(公告)日：2019-11-07

申请号：US15968562

申请日：2018-05-01

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Ian HU ,  Ming-Han WANG ,  Tsun-Lung Hsieh ,  Chih-Yi HUANG ,  Chih-Pin HUNG

IPC: H01L25/065 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package includes a substrate, an interposer disposed on the substrate, a conductive pillar disposed on the substrate, a first semiconductor device disposed on the interposer and electrically connected to the conductive pillar, a second semiconductor device disposed on the interposer, and an encapsulant surrounding the conductive pillar. The first semiconductor device includes a first conductive pad electrically connected to the interposer. The second semiconductor device includes a second conductive pad electrically connected to the interposer.

公开(公告)号：US20190244909A1

公开(公告)日：2019-08-08

申请号：US15891305

申请日：2018-02-07

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yong-Da CHIU ,  Shiu-Chih WANG ,  Shang-Kun HUANG ,  Ying-Ta CHIU ,  Shin-Luh TARNG ,  Chih-Pin HUNG

IPC: H01L23/532 ,  H01L23/00

CPC classification number: H01L23/53233 ,  H01L23/53238 ,  H01L24/06 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/161 ,  H05K2201/03 ,  H05K2201/09481

Abstract: A semiconductor package includes an electrical connection structure. The electrical connection structure includes: a first conductive layer; a second conductive layer on the first conductive layer; and a conductive cap between the first conductive layer and the second conductive layer, the conductive cap having a hardness greater than a hardness of the first conductive layer.