公开(公告)号：US20220020885A1

公开(公告)日：2022-01-20

申请号：US17488076

申请日：2021-09-28

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Pin TSAI ,  Tsung-Yueh TSAI ,  Teck-Chong LEE

IPC: H01L31/02 ,  H01L25/16 ,  H01L31/0203

Abstract: An optical device includes a first circuit layer, a light detector, a first conductive pillar and an encapsulant. The first circuit layer has an interconnection layer and a dielectric layer. The light detector is disposed on the first circuit layer. The light detector has a light detecting area facing away from the first circuit layer and a backside surface facing the first circuit layer. The first conductive pillar is disposed on the first circuit layer and spaced apart from the light detector. The first conductive pillar is electrically connected to the interconnection layer of the first circuit layer. The encapsulant is disposed on the first circuit layer and covers the light detector and the first conductive pillar. The light detector is electrically connected to the interconnection layer of the first circuit layer through the first conductive pillar. The backside surface of the light detector is exposed from the encapsulant.

公开(公告)号：US20210151398A1

公开(公告)日：2021-05-20

申请号：US16684353

申请日：2019-11-14

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun CHANG ,  Teck-Chong LEE ,  Sheng-Wen YANG

IPC: H01L23/00 ,  H01L23/31

Abstract: A semiconductor device package includes a first semiconductor device; a second semiconductor device; and a first redistribution layer disposed on the first semiconductor device and having a side wall defining an opening that exposes the first semiconductor device. The side wall of the first redistribution layer has an average surface roughness (Ra) in a range up to 2 micrometers (μm).

公开(公告)号：US20200083591A1

公开(公告)日：2020-03-12

申请号：US16544415

申请日：2019-08-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Sheng-Chi HSIEH ,  Chen-Chao WANG ,  Teck-Chong LEE ,  Chien-Hua CHEN

IPC: H01Q1/22 ,  H01L23/15 ,  H01L23/498 ,  H01L23/00 ,  H01L23/66 ,  H01L23/31 ,  H01L23/552 ,  H01L21/56 ,  H01L21/48 ,  H01L23/538 ,  H01Q9/16

Abstract: A semiconductor device package includes a glass carrier, a package body, a first circuit layer and a first antenna layer. The glass carrier has a first surface and a second surface opposite to the first surface. The package body is disposed on the first surface of the glass carrier. The package body has an interconnection structure penetrating the package body. The first circuit layer is disposed on the package body. The first circuit layer has a redistribution layer (RDL) electrically connected to the interconnection structure of the package body. The first antenna layer is disposed on the second surface of the glass carrier.

公开(公告)号：US20200075571A1

公开(公告)日：2020-03-05

申请号：US16560870

申请日：2019-09-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Teck-Chong LEE

IPC: H01L25/18 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L23/66

Abstract: A semiconductor device package includes a carrier, an electronic component, a protection layer, a conductive layer and an integrated passive device (IPD). The electronic component is disposed on the carrier. The protection layer covers the carrier and the electronic component. The conductive layer is disposed on the protection layer and penetrates the protection layer to be electrically connected to the electronic component. The IPD is disposed on the conductive layer and electrically connected to the electronic component through the conductive layer.

公开(公告)号：US20180337164A1

公开(公告)日：2018-11-22

申请号：US15599379

申请日：2017-05-18

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Hung-Yi LIN ,  Cheng-Yuan KUNG ,  Teck-Chong LEE ,  Shiuan-Yu LIN

IPC: H01L25/16 ,  H01L23/522 ,  H01L23/00 ,  H01L23/532 ,  H01L23/31

Abstract: A semiconductor device package includes a dielectric layer, a first RDL, a second RDL, an inductor, a first electronic component and a second electronic component. The first RDL is adjacent to a first surface of the dielectric layer, and the first RDL includes first conductive pieces. The second RDL is adjacent to a second surface of the dielectric layer, and the second RDL includes second conductive pieces. The inductor is disposed in the dielectric layer. The inductor includes induction pillars, wherein each of the induction pillars is disposed through the dielectric layer, and each of the induction pillars is interconnected between a respective one of the first conductive pieces of the first RDL and a respective one of the second conductive pieces of the second RDL. The first electronic component and the second electronic component are between the first RDL and the second RDL, and electrically connected to each other through the inductor.

公开(公告)号：US20130122216A1

公开(公告)日：2013-05-16

申请号：US13734621

申请日：2013-01-04

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Shin-Luh TARNG ,  Teck-Chong LEE

IPC: H05K3/00

CPC classification number: H05K3/0094 ,  B32B3/08 ,  B32B3/266 ,  B32B3/30 ,  B32B5/02 ,  B32B5/22 ,  B32B5/26 ,  B32B17/04 ,  B32B27/08 ,  B32B27/12 ,  B32B27/18 ,  B32B27/281 ,  B32B27/38 ,  B32B2255/00 ,  B32B2255/205 ,  B32B2260/021 ,  B32B2260/046 ,  B32B2262/101 ,  B32B2307/20 ,  B32B2307/202 ,  B32B2307/30 ,  B32B2307/718 ,  B32B2457/00 ,  H05K1/036 ,  H05K3/045 ,  H05K3/426 ,  H05K2201/0195 ,  H05K2201/029 ,  Y10T428/269

Abstract: A method of manufacturing an embedded-trace substrate is provided. First, a core plate is provided. Next, a through hole and a plurality of trenches are formed on the core plate, wherein the through hole passes through the core plate, and the trenches are formed on the upper and the lower surfaces of the core plate. Then, the core plate is subjected to one-plating step for electroplating a conductive material in the through hole and the trenches at the same time. Afterwards, the excess conductive material is removed.

Abstract translation: 提供一种制造嵌入式迹线衬底的方法。 首先，提供芯板。 接下来，在芯板上形成通孔和多个沟槽，其中通孔穿过芯板，并且沟槽形成在芯板的上表面和下表面上。 然后，对芯板进行一次镀步骤，同时对通孔和沟槽中的导电材料进行电镀。 之后，除去过量的导电材料。

公开(公告)号：US20250125209A1

公开(公告)日：2025-04-17

申请号：US19000635

申请日：2024-12-23

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun CHANG ,  Teck-Chong LEE

IPC: H01L23/31

Abstract: A semiconductor package structure includes a circuit pattern structure, an encapsulant and an anchoring structure. The encapsulant is disposed on the circuit pattern structure. The anchoring structure is disposed adjacent to an interface between the encapsulant and the circuit pattern structure, and is configured to reduce a difference between a variation of expansion of the encapsulant and a variation of expansion of the circuit pattern structure in an environment of temperature variation.

公开(公告)号：US20240178158A1

公开(公告)日：2024-05-30

申请号：US18434698

申请日：2024-02-06

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Po-Hsien KE ,  Teck-Chong LEE ,  Chih-Pin HUNG

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L23/3135 ,  H01L25/0652 ,  H01L25/50

Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device, a second electronic device, a first underfill, a second underfill and a stiff bonding material. The first electronic device and the second electronic device are disposed on the wiring structure, and are electrically connected to each other through the wiring structure. The first underfill is disposed in a first space between the first electronic device and the wiring structure. The second underfill is disposed in a second space between the second electronic device and the wiring structure. The stiff bonding material is disposed in a central gap between the first electronic device and the second electronic device. The stiff bonding material is different from the first underfill and the second underfill.

公开(公告)号：US20230261036A1

公开(公告)日：2023-08-17

申请号：US18139348

申请日：2023-04-25

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Chien-Hua CHEN ,  Teck-Chong LEE

IPC: H01L27/08 ,  H01L23/522

CPC classification number: H01L28/10 ,  H01L23/5227 ,  H01L23/522 ,  H01L23/5223 ,  H01L23/642

Abstract: A semiconductor device package includes a substrate, a first patterned conductive layer, a second patterned conductive layer, a dielectric layer, a third patterned conductive layer and a connector. The substrate has a top surface. The first patterned conductive layer is on the top surface of the substrate. The second patterned conductive layer contacts the first patterned conductive layer. The second patterned conductive layer includes a first portion, a second portion and a third portion. The second portion is connected between the first portion and the third portion. The dielectric layer is on the top surface of the substrate. The dielectric layer covers the first patterned conductive layer and surrounds the second portion and the third portion of the second patterned conductive layer. The first portion of the second patterned conductive layer is disposed on the dielectric layer. The third patterned conductive layer is on the second patterned conductive layer, and the connector is directly on the third patterned conductive layer.

公开(公告)号：US20230092252A1

公开(公告)日：2023-03-23

申请号：US17991814

申请日：2022-11-21

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yung-Shun CHANG ,  Meng-Wei HSIEH ,  Teck-Chong LEE

IPC: H01L23/522 ,  H01L21/56 ,  H01L21/768 ,  H01L23/31 ,  H01L23/00 ,  H01L23/528

Abstract: A semiconductor package structure includes a semiconductor die and at least one pillar structure. The semiconductor die has an upper surface and includes at least one conductive pad disposed adjacent to the upper surface. The pillar structure is electrically connected to the conductive pad of the semiconductor die, and defines a recess portion recessed from a side surface of the pillar structure. A conductivity of the pillar structure is greater than a conductivity of the conductive pad.