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公开(公告)号:US6097019A
公开(公告)日:2000-08-01
申请号:US129708
申请日:1998-08-05
CPC分类号: H05B6/806 , B01J19/126 , G01N22/00 , H05B6/6402 , H05B6/70 , H05B6/705 , B01J2219/00191 , H05B2206/046
摘要: A control system for a blind microwave radiation tool a workpiece is described. The controlled system automatically tunes the cavity containing the workpiece. The control system automatically controls the temperature of the workpiece according to a predetermined temperature versus time schedule. Control system automatically determines when the workpiece has reached a particular predetermined physical condition. To achieve these results the control system automatically monitors applied power, reflected power or current temperature and automatically controls the microwave cavity volume and shape and launch structure including antennae location, cavity short location, cavity diameter, coupling loop position, etc. in order to maintain the cavity in resonance and to determine when to exit without operator intervention. Control system can run on a small computer or an embedded controller and is useful for automatically curing polyamic acid to polyimide to a predetermined percent cure, processing preimpregnated glass cloth in a continuous manner which can be used in circuit boards and drying and partial curing of web-like materials automatically without operator intervention.
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公开(公告)号:US6010832A
公开(公告)日:2000-01-04
申请号:US441965
申请日:1995-05-16
CPC分类号: G03F7/037 , G03F7/0387 , Y10S430/107
摘要: Photosensitive compositions containing a polyimide precursor and a complex cation of a polymerizable carboxylic acid functional compound with a tertiary amino functional group; and use thereof to provide a pattern.
摘要翻译: 含有聚酰亚胺前体和具有叔氨基官能团的可聚合羧酸官能化合物的络合阳离子的光敏组合物; 并使用它来提供图案。
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23.
公开(公告)号:US5935687A
公开(公告)日:1999-08-10
申请号:US554009
申请日:1995-11-06
申请人: Evan Ezra Davidson , David Andrew Lewis , Jane Margaret Shaw , Alfred Viehbeck , Janusz Stanislaw Wilczynski
发明人: Evan Ezra Davidson , David Andrew Lewis , Jane Margaret Shaw , Alfred Viehbeck , Janusz Stanislaw Wilczynski
CPC分类号: H05K3/4641 , H01L25/0652 , H05K1/145 , H01L2224/48091 , H01L2924/01014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/10253 , H01L2924/19041 , H05K1/053 , H05K1/056 , H05K2201/068 , H05K2201/09309 , H05K2201/09718 , H05K3/3436 , H05K3/4608 , Y10S428/901 , Y10T428/24802 , Y10T428/24917 , Y10T428/24926
摘要: A three dimensional packaging architecture for ultimate high performance computers and methods for fabricating thereof are described. The package allows very dense packaging of multiple integrated circuit chips for minimum communication distances and maximum clock speeds of the computer. The packaging structure is formed from a plurality of subassemblies. Each subassembly is formed from a substrate which has on at least one side thereof at least one integrated circuit device. Between adjacent subassemblies there is disposed a second substrate. There are electrical interconnection means to electrically interconnect contact locations on the subassembly to contact locations on the second substrate. The electrical interconnection means can be solder mounds, wire bonds and the like. The first substrate provides electrical signal intercommunication between the electronic devices and each subassembly. The second substrate provides ground and power distribution to the plurality of subassemblies. Optionally, the outer surfaces of the structure that can be disposed a cube of memory chips.
摘要翻译: 描述了用于最终高性能计算机的三维封装架构及其制造方法。 该封装允许非常密集的多个集成电路芯片的封装,以实现计算机的最小通信距离和最大时钟速度。 包装结构由多个子组件形成。 每个子组件由至少一个侧面上至少有一个集成电路器件的衬底形成。 在相邻的子组件之间设置有第二衬底。 存在用于将子组件上的接触位置电互连到第二基板上的接触位置的电互连装置。 电互连装置可以是焊锡槽,引线接合等。 第一基板在电子设备和每个子组件之间提供电信号互通。 第二基板提供对多个子组件的接地和功率分配。 可选地,结构的外表面可以设置成存储芯片的立方体。
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24.
公开(公告)号:US06730618B2
公开(公告)日:2004-05-04
申请号:US10137009
申请日:2002-05-01
IPC分类号: H01L2131
CPC分类号: H01L21/02118 , H01L21/02115 , H01L21/28194 , H01L21/312 , H01L21/3121 , H01L21/3146 , H01L23/53228 , H01L23/5329 , H01L29/513 , H01L29/517 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要: An interlayer dielectric for preventing Cu ion migration in semiconductor structure containing a Cu region is provided. The interlayer dielectric of the present invention comprises a dielectric material that has a dielectric constant of 3.0 or less and an additive which is highly-capable of binding Cu ions, yet is soluble in the dielectric material. The presence of the additive in the low k dielectric allows for the elimination of conventional inorganic barrier materials such as SiO2 or Si3N4.
摘要翻译: 提供了一种用于防止含有Cu区域的半导体结构中的Cu离子迁移的层间电介质。 本发明的层间电介质包括介电常数为3.0以下的介电材料和能够结合Cu离子的添加剂,但是其可溶于电介质材料。 添加剂在低k电介质中的存在允许消除常规的无机阻挡材料如SiO 2或Si 3 N 4。
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公开(公告)号:US06437422B1
公开(公告)日:2002-08-20
申请号:US09852078
申请日:2001-05-09
申请人: Paul M. Solomon , Jane Margaret Shaw , Cherie R. Kagan , Christos Dimitrios Dimitrakopoulos , Tak Hung Ning
发明人: Paul M. Solomon , Jane Margaret Shaw , Cherie R. Kagan , Christos Dimitrios Dimitrakopoulos , Tak Hung Ning
IPC分类号: H01L2906
CPC分类号: D02G3/441 , H01L29/0657 , H01L51/0036 , H01L51/0512 , H02N2/18
摘要: Active devices that have either a thread or a ribbon geometry. The thread geometry includes single thread active devices and multiple thread devices. Single thread devices have a central core that may contain different materials depending upon whether the active device is responsive to electrical, light, mechanical, heat, or chemical energy. Single thread active devices include FETs, electro-optical devices, stress transducers, and the like. The active devices include a semiconductor body that for the single thread devices is a layer about the core of the thread. For the multiple thread devices, the semiconductor body is either a layer on one or more of the threads or an elongated body disposed between two of the threads. For example, a FET is formed of three threads, one of which carries a gate insulator layer and a semiconductor layer and the other two of which are electrically conductive and serve as the source and drain. The substrates or threads are preferably flexible and can be formed in a fabric.
摘要翻译: 具有螺纹或带状几何形状的活动设备。 螺纹几何包括单线程有源器件和多线程器件。 单线设备具有中心芯,其可以包含不同的材料,这取决于有源器件是否响应于电,光,机械,热或化学能量。 单线有源器件包括FET,电光器件,应力传感器等。 有源器件包括用于单线器件是围绕线芯的层的半导体本体。 对于多线器件,半导体本体是一个或多个螺纹上的层或设置在两个螺纹之间的细长体。 例如,FET由三条线构成,其中一条带有栅极绝缘体层和半导体层,另外两条导电并用作源极和漏极。 基材或丝线优选是柔性的并且可以在织物中形成。
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26.
公开(公告)号:US06268238B1
公开(公告)日:2001-07-31
申请号:US09111507
申请日:1998-07-08
申请人: Evan Ezra Davidson , David Andrew Lewis , Jane Margaret Shaw , Alfred Viehbeck , Janusz Stanislaw Wilczynski
发明人: Evan Ezra Davidson , David Andrew Lewis , Jane Margaret Shaw , Alfred Viehbeck , Janusz Stanislaw Wilczynski
IPC分类号: H01L2144
CPC分类号: H05K3/4641 , H01L25/0652 , H01L2224/48091 , H01L2924/01014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/10253 , H01L2924/19041 , H05K1/053 , H05K1/056 , H05K1/145 , H05K3/3436 , H05K3/4608 , H05K2201/068 , H05K2201/09309 , H05K2201/09718 , Y10S428/901 , Y10T428/24802 , Y10T428/24917 , Y10T428/24926 , H01L2924/00014 , H01L2924/00
摘要: A three dimensional packaging architecture for ultimate high performance computers and methods for fabricating thereof are described. The packgage allows very dense packaging of multiple integrated circuit chips for minimum communication distances and maximum clock speeds of the computer. The packaging structure is formed from a plurality of subassemblies. Each subassembly is formed from a substrate which has on at least one side thereof at least one integrated circuit device. Between adjacent subassemblies there is disposed a second substrate. There are electrical interconnection means to electrically interconnect contact locations on the subassembly to contact locations on the second substrate. The electrical interconnection means can be solder mounds, wire bonds and the like. The first substrate provides electrical signal intercommunication between the electronic devices and each subassembly. The second substrate provides ground and power distribution to the plurality of subassemblies. Optionally, the outer surfaces of the structure that can be disposed a cube of memory chips.
摘要翻译: 描述了用于最终高性能计算机的三维封装架构及其制造方法。 该包装允许非常密集的多个集成电路芯片的封装,以实现计算机的最小通信距离和最大时钟速度。 包装结构由多个子组件形成。 每个子组件由至少一个侧面上至少有一个集成电路器件的衬底形成。 在相邻的子组件之间设置有第二衬底。 存在用于将子组件上的接触位置电互连到第二基板上的接触位置的电互连装置。 电互连装置可以是焊锡槽,引线接合等。 第一基板在电子设备和每个子组件之间提供电信号互通。 第二基板提供对多个子组件的接地和功率分配。 可选地,结构的外表面可以设置成存储芯片的立方体。
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公开(公告)号:US5817986A
公开(公告)日:1998-10-06
申请号:US699954
申请日:1996-08-20
申请人: Evan Ezra Davidson , David Andrew Lewis , Jane Margaret Shaw , Alfred Viehbeck , Janusz Stanislaw Wilczynski
发明人: Evan Ezra Davidson , David Andrew Lewis , Jane Margaret Shaw , Alfred Viehbeck , Janusz Stanislaw Wilczynski
CPC分类号: H05K3/4641 , H01L25/0652 , H05K1/145 , H01L2224/48091 , H01L2924/01014 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/10253 , H01L2924/19041 , H05K1/053 , H05K1/056 , H05K2201/068 , H05K2201/09309 , H05K2201/09718 , H05K3/3436 , H05K3/4608 , Y10S428/901 , Y10T428/24802 , Y10T428/24917 , Y10T428/24926
摘要: A three dimensional packaging architecture for ultimate high performance computers and methods for fabricating thereof are described. The package allows very dense packaging of multiple integrated circuit chips for minimum communication distances and maximum clock speeds of the computer. The packaging structure is formed from a plurality of subassemblies. Each subassembly is formed from a substrate which has on at least one side thereof at least one integrated circuit device. Between adjacent subassemblies there is disposed a second substrate. There are electrical interconnection means to electrically interconnect contact locations on the subassembly to contact locations on the second substrate. The electrical interconnection means can be solder mounds, wire bonds and the like. The first substrate provides electrical signal intercommunication between the electronic devices and each subassembly. The second substrate provides ground and power distribution to the plurality of subassemblies. Optionally, the outer surfaces of the structure that can be disposed a cube of memory chips.
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