公开(公告)号：US20190377599A1

公开(公告)日：2019-12-12

申请号：US16005811

申请日：2018-06-12

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA ,  Chris ABERNATHY ,  Michael FILIPPO

IPC: G06F9/48 ,  G06F9/38 ,  G06F9/30

Abstract: There is provided a data processing apparatus that includes processing circuitry for executing a plurality of instructions. Storage circuitry stores a plurality of entries, each entry relating to an instruction in the plurality of instructions and including a dependency field. The dependency field stores a data dependency of that instruction on a previous instruction in the plurality of instructions. Scheduling circuitry schedules the execution of the plurality of instructions in an order that depends on each data dependency. When the previous instruction is a single-cycle instruction, the dependency field includes a reference to one of the entries that relates to the previous instruction, otherwise, the data dependency field includes an indication of an output destination of the previous instruction.

公开(公告)号：US20180225232A1

公开(公告)日：2018-08-09

申请号：US15427391

申请日：2017-02-08

Applicant: ARM Limited

Inventor： Michael FILIPPO ,  Jamshed JALAL ,  Klas Magnus BRUCE ,  Paul Gilbert MEYER ,  David Joseph HAWKINS ,  Phanindra Kumar MANNAVA ,  Joseph Michael PUSDESRIS

IPC: G06F13/16 ,  G06F13/364 ,  G06F12/0864 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/1642 ,  G06F12/0833 ,  G06F12/0844 ,  G06F12/0864 ,  G06F13/1668 ,  G06F13/364 ,  G06F13/404 ,  G06F13/4282 ,  G06F2212/6032 ,  G06F2212/621

Abstract: A memory controller comprises memory access circuitry configured to initiate a data access of data stored in a memory in response to a data access hint message received from another node in data communication with the memory controller; to access data stored in the memory in response to a data access request received from another node in data communication with the memory controller and to provide the accessed data as a data access response to the data access request.

公开(公告)号：US20180107606A1

公开(公告)日：2018-04-19

申请号：US15294031

申请日：2016-10-14

Applicant: ARM LIMITED

Inventor： Barry Duane WILLIAMSON ,  Michael FILIPPO ,  . ABHISHEK RAJA ,  Adrian MONTERO ,  Miles Robert DOOLEY

IPC: G06F12/1045 ,  G06F12/128 ,  G06F12/1009

CPC classification number: G06F12/1063 ,  G06F12/1009 ,  G06F12/128 ,  G06F2212/621 ,  G06F2212/68 ,  G06F2212/69

Abstract: A data processing system 2 includes an address translation cache 12 to store a plurality of address translation entries. Eviction control circuitry 10 selects a victim entry for eviction from address translation cache 12 using an eviction control parameter. The address translation cache 12 can store multiple different types of entry corresponding to respective different levels of address translation within a multiple-level page table walk. The different types of entry have different eviction control parameters assigned at the time of allocation. Eviction from the address translation cache is dependent upon the entry type, as well as the subsequent accesses to the entry concerned and the other entries within the address translation cache.

公开(公告)号：US20180095893A1

公开(公告)日：2018-04-05

申请号：US15281502

申请日：2016-09-30

Applicant: ARM LIMITED

Inventor： Miles Robert DOOLEY ,  Matthew Andrew RAFACZ ,  Huzefa Moiz SANJELIWALA ,  Michael FILIPPO

IPC: G06F12/1045 ,  G06F12/0862 ,  G06F12/0897

CPC classification number: G06F12/1045 ,  G06F9/30 ,  G06F9/3016 ,  G06F12/0862 ,  G06F12/0897 ,  G06F2212/1016 ,  G06F2212/50 ,  G06F2212/602

Abstract: A data processing apparatus is provided including queue circuitry to respond to control signals each associated with a memory access instruction, and to queue a plurality of requests for data, each associated with a reference to a storage location. Resolution circuitry acquires a request for data, and issues the request for data, the resolution circuitry having a resolution circuitry limit. When a current capacity of the resolution circuitry is below the resolution circuitry limit, the resolution circuitry acquires the request for data by receiving the request for data from the queue circuitry, stores the request for data in association with the storage location, issues the request for data, and causes a result of issuing the request for data to be provided to said storage location. When the current capacity of the resolution circuitry meets or exceeds the resolution circuitry limit, the resolution circuitry acquires the request for data by examining a next request for data in the queue circuitry and issues a further request for the data based on the request for data.

公开(公告)号：US20180095752A1

公开(公告)日：2018-04-05

申请号：US15281226

申请日：2016-09-30

Applicant: ARM LIMITED

Inventor： Vasu KUDARAVALLI ,  Matthew Paul ELWOOD ,  Adam GEORGE ,  Muhammad Umar FAROOQ ,  Michael FILIPPO

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875

CPC classification number: G06F12/0875 ,  G06F8/41 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3017 ,  G06F9/30196 ,  G06F9/3808 ,  G06F9/382 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3846 ,  G06F9/3848 ,  G06F2212/452

Abstract: An apparatus comprises processing circuitry, an instruction cache, decoding circuitry to decode program instructions fetched from the cache to generate macro-operations to be processed by the processing circuitry, and predecoding circuitry to perform a predecoding operation on a block of program instructions fetched from a data store to generate predecode information to be stored to the cache with the block of instructions. In one example the predecoding operation comprises generating information on how many macro-operations are to generated by the decoding circuitry for a group of one or more program instructions. In another example the predecoding operation comprises generating information indicating whether at least one of a given subset of program instructions within the prefetched block is a branch instruction.