公开(公告)号：US20220334429A1

公开(公告)日：2022-10-20

申请号：US16964106

申请日：2019-09-03

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Wenqu LIU ,  Qi YAO ,  Feng ZHANG ,  Zhijun LV ,  Liwen DONG ,  Xiaoxin SONG ,  Zhao CUI ,  Detian MENG ,  Libo WANG ,  Jifeng TAN ,  Xiandong MENG

IPC: G02F1/1335 ,  G02F1/1343 ,  G02F1/1333 ,  G02F1/137 ,  G02F1/1337 ,  F21V8/00

Abstract: The embodiments of the present disclosure provide a display panel. The display panel includes a first substrate, a second substrate disposed opposite to the first substrate, and a liquid crystal layer between the first substrate and the second substrate, a plurality of first electrodes disposed on a side, close to the second substrate, of the first substrate and spaced apart at intervals, a first dielectric layer for planarizing the plurality of first electrodes, a second dielectric layer disposed on a side, close to the liquid crystal layer, of the first dielectric layer, a light shielding portion disposed on the side, close to the liquid crystal layer, of the second substrate, and a control circuit configured to apply a voltage between the first electrode and the second electrode so that the liquid crystal layer is in a first state or a second state.

公开(公告)号：US20220035503A1

公开(公告)日：2022-02-03

申请号：US17242511

申请日：2021-04-28

Applicant: BOE Technology Group Co., Ltd.

Inventor： Wenqu LIU ,  Qi YAO ,  Feng ZHANG ,  Zhao CUI ,  Libo WANG ,  Dongfei HOU ,  Xiaoxin SONG ,  Zhijun LV ,  Liwen DONG ,  Detian MENG ,  Jaiil RYU ,  Yang YUE ,  Haitao HUANG

IPC: G06F3/041 ,  G06F3/045 ,  G06F3/044 ,  G06K9/00

Abstract: The present disclosure provides a fingerprint recognition unit and a fabrication method thereof, a fingerprint recognition module and a display device. The fingerprint recognition unit includes: a bearing substrate; a receiving electrode layer on the bearing substrate; a piezoelectric material layer on a side of the receiving electrode layer away from the bearing substrate; and a driving electrode layer on a side of the piezoelectric material layer away from the receiving electrode layer. A density of the driving electrode layer is greater than 5 g/cm3, and a thickness of the driving electrode layer, a thickness of the piezoelectric material layer and a thickness of the bearing substrate are configured such that a vibration nodal plane of the piezoelectric material layer is within the piezoelectric material layer.

公开(公告)号：US20210385583A1

公开(公告)日：2021-12-09

申请号：US17288947

申请日：2020-05-29

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhao CUI ,  Feng ZHANG ,  Wenqu LIU ,  Liwen DONG ,  Zhijun LV ,  Xiaoxin SONG ,  Detian MENG ,  Libo WANG ,  Qi YAO

IPC: H04R17/00 ,  H04R3/00 ,  H04R31/00 ,  H01L41/047 ,  H01L41/193

Abstract: A transducer, a method of manufacturing a transducer, and a transducing device are provided. The transducer includes a receiving unit and a transmitting unit. The receiving unit includes a first receiving electrode, a first piezoelectric film, and a second receiving electrode which are sequentially stacked, and the receiving unit is configured to convert a first acoustic wave signal into an electrical signal by using a piezoelectric effect of the first piezoelectric film. The transmitting unit is configured to receive a control signal, which is based on the electrical signal, to transmit a second acoustic wave signal.

公开(公告)号：US20210225877A1

公开(公告)日：2021-07-22

申请号：US16772272

申请日：2019-12-19

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yanan NIU ,  Kuanjun PENG ,  Jiushi WANG ,  Zhanfeng CAO ,  Feng ZHANG ,  Qi YAO ,  Wusheng LI ,  Feng GUAN ,  Lei CHEN ,  Jintao PENG ,  Tingting ZHOU

IPC: H01L27/12

Abstract: The present disclosure provides a display substrate and a manufacturing method thereof, and a display device. In the display substrate of the present disclosure, a first transistor comprises a first gate electrode, a first electrode, a second electrode, and a first active layer; and a second transistor comprises a second gate electrode, a third electrode, a fourth electrode, and a second active layers, wherein the first active layer comprises a silicon material, the second active layer comprises an oxide semiconductor material, and wherein the third electrode and the first gate electrode are disposed in the same layer, and the fourth electrode and the first electrode, the second electrodes are disposed in the same layer.

公开(公告)号：US20190198592A1

公开(公告)日：2019-06-27

申请号：US16326787

申请日：2018-05-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Feng ZHANG ,  Zhijun LV ,  Wenqu LIU ,  Liwen DONG ,  Shizheng ZHANG ,  Ning DANG

IPC: H01L27/32 ,  H01L51/52 ,  H01L51/56

CPC classification number: H01L27/3248 ,  H01L51/52 ,  H01L51/5271 ,  H01L51/56 ,  H01L2227/32 ,  H01L2251/50 ,  H01L2251/56

Abstract: The present disclosure provides an OLED substrate and a manufacturing method thereof, a display device and a manufacturing method thereof, and belongs to the technical field of display technology. A manufacturing method for an OLED substrate of the present disclosure includes: forming, by a patterning process, a pattern including first electrodes of OLED devices and a pixel defining layer provided above the first electrodes above the base substrate, wherein the pixel defining layer includes a plurality of pixel partition walls spaced apart from each other, each of the pixel partition walls defines one of the first electrodes.

公开(公告)号：US20160372698A1

公开(公告)日：2016-12-22

申请号：US14906260

申请日：2015-07-20

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Yonglian QI ,  Feng ZHANG ,  Dongfang WANG

IPC: H01L51/52 ,  H01L51/56 ,  H01L27/32

CPC classification number: H01L51/5228 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/3258 ,  H01L29/7869 ,  H01L51/5218 ,  H01L51/5234 ,  H01L51/56 ,  H01L2227/323 ,  H01L2251/5353

Abstract: The present invention relates to an array substrate, a fabricating method thereof, and a display device. The array substrate comprises a thin film transistor, an auxiliary electrode which is arranged in a same layer as an active layer of the thin film transistor, and a transparent cathode which is electrically connected with the auxiliary electrode, wherein the active layer is an oxide semiconductor, and the auxiliary electrode is an electric conductor which is formed by performing a modification treatment on the oxide semiconductor. According to technical solutions of the present invention, the active layer and the auxiliary electrode are arranged in a same layer, a pattern of the active layer and the auxiliary electrode can be formed by a same etching process, and a separate process for forming the auxiliary electrode is not required, thus reducing the overall process time of the array substrate and saving the fabricating cost. (FIG. 1)

Abstract translation: 本发明涉及一种阵列基板及其制造方法以及显示装置。 阵列基板包括薄膜晶体管，与薄膜晶体管的有源层相同的层布置的辅助电极和与辅助电极电连接的透明阴极，其中有源层是氧化物半导体 辅助电极是通过对氧化物半导体进行改性处理而形成的导电体。 根据本发明的技术方案，有源层和辅助电极配置在相同的层中，有源层和辅助电极的图形可以通过相同的蚀刻工艺形成，并且用于形成辅助层 电极不需要，从而减少阵列基板的整个工艺时间并节省制造成本。 （图。1）

公开(公告)号：US20160351588A1

公开(公告)日：2016-12-01

申请号：US15233255

申请日：2016-08-10

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Shi SHU ,  Feng ZHANG ,  Yaohui GU ,  Fang HE ,  Feng GU

IPC: H01L27/12 ,  H01L29/45 ,  G02F1/1368 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1335 ,  G02F1/1339 ,  H01L21/768 ,  G02F1/1333

CPC classification number: H01L27/124 ,  G02F1/133345 ,  G02F1/133516 ,  G02F1/13394 ,  G02F1/134363 ,  G02F1/13439 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2001/136222 ,  G02F2001/136295 ,  G02F2201/121 ,  G02F2201/123 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/1288 ,  H01L29/458

Abstract: Embodiments of the disclosure disclose an array substrate and a fabrication method thereof, and a display device. The fabrication method of the array substrate comprises: forming a thin film transistor; forming a passivation layer covering the thin film transistor, the passivation layer having a via hole and the via hole exposing at least a portion of a drain electrode of the thin film transistor; forming a via-hole conductive layer, the via-hole conductive layer covering the portion of the drain electrode exposed at the via hole and connected to the drain electrode; treating the via-hole conductive layer, so that a reflectivity of the via-hole conductive layer is lower than a reflectivity of the drain electrode; and forming a pixel electrode, the pixel electrode being connected with the drain electrode through the via-hole conductive layer.

Abstract translation: 本发明的实施例公开了阵列基板及其制造方法以及显示装置。 阵列基板的制造方法包括：形成薄膜晶体管; 形成覆盖所述薄膜晶体管的钝化层，所述钝化层具有通孔，所述通孔暴露所述薄膜晶体管的漏电极的至少一部分; 形成通孔导电层，所述通孔导电层覆盖在所述通孔露出并与所述漏电极连接的所述漏电极的所述部分; 处理通孔导电层，使得通孔导电层的反射率低于漏电极的反射率; 并且形成像素电极，所述像素电极通过所述通孔导电层与所述漏电极连接。

公开(公告)号：US20160351585A1

公开(公告)日：2016-12-01

申请号：US14895352

申请日：2015-05-15

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Zhanfeng CAO ,  Feng ZHANG ,  Qi YAO ,  Jincheng GAO ,  Bin ZHANG ,  Xiaolong HE ,  Zhengliang LI ,  Wei ZHANG

IPC: H01L27/12 ,  G02F1/1345

CPC classification number: H01L27/124 ,  G02F1/1345 ,  G02F1/13452 ,  G02F1/13454 ,  G02F1/136204 ,  H01L27/12

Abstract: An array substrate and a display device are provided. The array substrate comprises a plurality of signal lines (40), a plurality of connecting lines (50) and a driving module (60) in a peripheral region (1) outside a display region (2); the connecting lines (50) are configured for connecting the signal lines (40) and the driving module (60), to transmit signal from the signal lines (40) to the driving module (60), wherein, at least one of the connecting lines (50) and at least one of the signal lines (40) are designed to intersect with and insulated from each other in a first region (N). The at least one of the signal lines (40) includes, in a second region (O) other than the first region (N), a first electrode line layer (401) and a second electrode line layer (402), while, in the first region (N), includes the first electrode line layer (401) but does not include the second electrode line layer (402). The array substrate may prevent problems of electrostatic accumulation or short circuit from occurring between the connecting lines (50) and the second electrode line layer (402).

Abstract translation: 提供阵列基板和显示装置。 阵列基板包括在显示区域（2）外部的周边区域（1）中的多条信号线（40），多条连接线（50）和驱动模块（60）。 连接线（50）被配置用于连接信号线（40）和驱动模块（60），以将信号从信号线（40）发送到驱动模块（60），其中至少一个连接 线路（50）和信号线（40）中的至少一个被设计成在第一区域（N）中与彼此相交和绝缘。 信号线（40）中的至少一个在除了第一区域（N）之外的第二区域（O）中包括第一电极线层（401）和第二电极线层（402），而在 第一区域（N）包括第一电极线层（401），但不包括第二电极线层（402）。 阵列基板可以防止在连接线（50）和第二电极线层（402）之间发生静电积聚或短路的问题。

公开(公告)号：US20160293875A1

公开(公告)日：2016-10-06

申请号：US14369653

申请日：2013-12-04

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Feng ZHANG ,  Qi YAO

IPC: H01L51/50 ,  H01L51/56 ,  H01L51/52 ,  H01L27/32

Abstract: The present invention provides a method for manufacturing a quantum dot light-emitting element and a display device. The method comprises mixing a quantum dot light-emitting material and a hole-transporting material or mixing the quantum dot light-emitting material and an electron-transporting material, and dissolving a mixture into an organic solvent to form a mixed solvent, applying the mixed solvent to a substrate for manufacturing a quantum dot light-emitting element, removing the organic solvent form the mixed solvent to stratify the quantum dot light-emitting material and the hole-transporting material or the electron-transporting material on the substrate for manufacturing a quantum dot light-emitting element to form a quantum dot light-emitting layer and a hole-transporting layer or an electron-transporting layer.

Abstract translation: 本发明提供一种量子点发光元件和显示装置的制造方法。 该方法包括混合量子点发光材料和空穴传输材料或混合量子点发光材料和电子传输材料，并将混合物溶解在有机溶剂中以形成混合溶剂，将混合的 溶剂施加到用于制造量子点发光元件的基板，从混合溶剂中除去有机溶剂，以将量子点发光材料和空穴传输材料或电子传输材料分层在制造量子基板上 点阵发光元件形成量子点发光层和空穴传输层或电子传输层。

公开(公告)号：US20160254388A1

公开(公告)日：2016-09-01

申请号：US14768992

申请日：2014-11-27

Applicant: BOE Technology Group Co., Ltd

Inventor： Feng ZHANG ,  Zhanfeng CAO ,  Qi YAO

IPC: H01L29/786 ,  H01L29/66 ,  G02F1/1368 ,  H01L27/12

CPC classification number: H01L29/78606 ,  G02F1/1368 ,  G02F2201/40 ,  H01L21/76801 ,  H01L21/76829 ,  H01L21/76831 ,  H01L27/1225 ,  H01L27/127 ,  H01L29/41733 ,  H01L29/66765 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869 ,  H01L29/78696 ,  H01L51/0529

Abstract: A thin film transistor is disclosed in the present invention. The thin film transistor comprises: a substrate, an active layer, a first etching barrier layer, a second etching barrier layer, a source and a drain, wherein: the active layer is disposed over the substrate; the first etching barrier layer is disposed over the active layer; the second etching barrier layer is disposed over the first etching barrier layer; the source and the drain are disposed over the second etching barrier layer, and are connected to each other through the active layer by means of via holes formed in the first etching barrier layer and the second etching barrier layer by etching; and a length of the first etching barrier layer at a channel position is less than a length of the second etching barrier layer. A method of manufacturing the thin film transistor, an array substrate and a display apparatus are also disclosed in the present invention. A length of a channel of the thin film transistor according to the present invention is less than the length of the channel of the conventional thin film transistor. Thereby, size and energy consumption of the thin film transistor are reduced, an aperture ratio of a liquid crystal panel is increased, and a turn-on current of the thin film transistor is increased, so that whole performance of the thin film transistor is further improved.

Abstract translation: 在本发明中公开了一种薄膜晶体管。 薄膜晶体管包括：衬底，有源层，第一蚀刻阻挡层，第二蚀刻阻挡层，源极和漏极，其中：有源层设置在衬底上; 第一蚀刻阻挡层设置在有源层上; 所述第二蚀刻阻挡层设置在所述第一蚀刻阻挡层上; 源极和漏极设置在第二蚀刻阻挡层之上，并且通过通过蚀刻在第一蚀刻阻挡层和第二蚀刻阻挡层中形成的通孔而通过有源层彼此连接; 并且沟道位置处的第一蚀刻阻挡层的长度小于第二蚀刻阻挡层的长度。 在本发明中还公开了制造薄膜晶体管，阵列基板和显示装置的方法。 根据本发明的薄膜晶体管的沟道的长度小于常规薄膜晶体管的沟道的长度。 因此，薄膜晶体管的尺寸和能量消耗减小，液晶面板的开口率增加，薄膜晶体管的导通电流增加，薄膜晶体管的整体性能进一步提高 改进。