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    Auto-zero current sensing amplifier
    21.
    发明授权
    Auto-zero current sensing amplifier 有权
    自动零电流检测放大器

    公开(公告)号：US07724596B1

    公开(公告)日：2010-05-25

    申请号：US12209577

    申请日：2008-09-12

    Applicant: Pantas Sutardja ,  Yonghua Song ,  Bo Wang ,  Chih-Hsin Wang ,  Qiang Tang

    Inventor： Pantas Sutardja ,  Yonghua Song ,  Bo Wang ,  Chih-Hsin Wang ,  Qiang Tang

    IPC: G11C7/02 ,  H03F3/45

    CPC classification number: G11C16/28 ,  G11C7/062 ,  G11C2207/063

    Abstract: A sensing amplifier for a memory cell comprises a selection stage that outputs one of a reference current and a memory cell current during a first period and the other of the reference current and the memory cell current during a second period. The first period and the second period are non-overlapping. An input stage generates a first current based on the one of the reference current and the memory cell current during the first period and generates a second current based on the other of the reference current and the memory cell current during the second period. A sensing stage senses a first value based on the first current and stores the first value during the first period, senses a second value based on the second current during the second period and compares the first value to the second value.

    Abstract translation: 用于存储单元的感测放大器包括选择级，其在第一时段期间输出参考电流和存储单元电流之一，并且在第二时段期间输出参考电流和存储单元电流中的另一个。 第一期与第二期不重叠。 输入级在第一时段期间基于参考电流和存储单元电流之一产生第一电流，并且在第二周期期间基于参考电流和存储单元电流中的另一个产生第二电流。 感测级基于第一电流感测第一值并且在第一周期期间存储第一值，在第二周期期间基于第二电流感测第二值，并将第一值与第二值进行比较。

    ALIGNMENT PROTECTION IN NON-VOLATILE MEMORY AND ARRAY
    23.
    发明申请
    ALIGNMENT PROTECTION IN NON-VOLATILE MEMORY AND ARRAY 审中-公开
    非易失性存储器和阵列中的对准保护

    公开(公告)号：US20080237696A1

    公开(公告)日：2008-10-02

    申请号：US11933377

    申请日：2007-10-31

    Applicant: Chih-Hsin Wang

    Inventor： Chih-Hsin Wang

    IPC: H01L29/786

    CPC classification number: H01L27/11568 ,  G11C16/0416 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11534 ,  H01L29/40114 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

    Abstract: A memory device, a memory array and a method of arranging memory devices and arrays. The memory device includes a memory region including a plurality of memory cells, each memory cell with a source, a drain and a channel between the source and the drain, a channel dielectric, a charge storage region and an electrically alterable conductor-material system in proximity to the charge storage region. The memory device includes a plurality of conductor lines. The memory includes a non-memory region having embedded logic including a plurality of transistors, each transistor for electrically coupling one of the conductor lines and each transistor including a transistor source, a transistor drain and a transistor gate.

    Abstract translation: 存储器件，存储器阵列和布置存储器件和阵列的方法。 存储器件包括存储器区域，其包括多个存储器单元，每个存储单元具有源极，漏极和源极与漏极之间的沟道，沟道电介质，电荷存储区域和电可改变的导体材料系统 靠近电荷存储区域。 存储器件包括多条导体线。 存储器包括具有包括多个晶体管的嵌入逻辑的非存储区域，用于电耦合导体线之一的每个晶体管和包括晶体管源，晶体管漏极和晶体管栅极的每个晶体管。

    Low power electrically alterable nonvolatile memory cells and arrays
    24.
    发明申请
    Low power electrically alterable nonvolatile memory cells and arrays 有权
    低功率电气可变非易失性存储器单元和阵列

    公开(公告)号：US20080061321A1

    公开(公告)日：2008-03-13

    申请号：US11978875

    申请日：2007-10-30

    Applicant: Chih-Hsin Wang

    Inventor： Chih-Hsin Wang

    IPC: H01L21/336 ,  H01L21/82 ,  H01L27/10

    CPC classification number: H01L27/11568 ,  G11C16/0416 ,  G11C16/0466 ,  H01L21/26586 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/47 ,  H01L29/66636 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/7883 ,  H01L29/792

    Abstract: A method of providing a memory cell includes providing a body of a semiconductor material having a first conductivity type, arranging a filter of a conductor-filter system in contact with a first conductor of the conductor-filter system, arranging at least portion of a second conductor of a conductor-insulator system in contact with the filter, arranging a first insulator of the conductor-insulator system in contact with the second conductor at an interface, arranging a first region spaced from the second conductor, arranging a channel of the body between the first region and the second conductor, arranging a second insulator adjacent to the first region, arranging a charge storage region between the first and the second insulators, arranging a first portion of a word-line adjacent to and insulated from the charge storage region, and arranging a second portion of the word-line adjacent to and insulated from the body.

    Abstract translation: 提供存储单元的方法包括提供具有第一导电类型的半导体材料的主体，布置与导体过滤器系统的第一导体接触的导体过滤系统的滤波器，将至少部分第二导体 与过滤器接触的导体 - 绝缘体系统的导体，在接口处布置导体 - 绝缘体系统的第一绝缘体与第二导体接触，布置与第二导体间隔开的第一区域，将主体的沟道布置在 所述第一区域和所述第二导体布置与所述第一区域相邻的第二绝缘体，在所述第一绝缘体和所述第二绝缘体之间布置电荷存储区域，布置与所述电荷存储区域相邻并与所述电荷存储区域绝缘的字线的第一部分， 并且将所述字线的第二部分布置成与所述主体相邻并且与所述主体绝缘。

    Electrically alterable non-volatile memory cell
    26.
    发明授权
    Electrically alterable non-volatile memory cell 失效
    电可变非易失性存储单元

    公开(公告)号：US07098499B2

    公开(公告)日：2006-08-29

    申请号：US10919555

    申请日：2004-08-16

    Applicant: Chih-Hsin Wang

    Inventor： Chih-Hsin Wang

    IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC classification number: G11C16/14 ,  G11C16/0416 ,  H01L29/42332 ,  H01L29/7885 ,  H01L29/792

    Abstract: A nonvolatile memory cell is provided. The memory cell includes a storage transistor and an injector in a well of an n-type conductivity. The well is formed in a semiconductor substrate of a p-type conductivity. The storage transistor comprises a source, a drain, a channel, and a charge storage region. The source and the drain are formed in the well and having the p-type conductivity with the channel of the well defined therebetween. The charge storage region is disposed over and insulated from the channel region by an insulator. Further provided are methods operating the memory cell, including means for injecting electrons from the channel through the insulator onto the charge storage region and means for injecting holes from the injector through the well through the channel through the insulator onto the charge storage region. The memory cell can be implemented in a conventional logic CMOS process.

    Abstract translation: 提供非易失性存储单元。 存储单元包括n型导电性阱中的存储晶体管和注入器。 该阱形成在p型导电性的半导体衬底中。 存储晶体管包括源极，漏极，沟道和电荷存储区域。 源极和漏极形成在阱中并且具有p型导电性，阱之间的沟道被限定。 电荷存储区域通过绝缘体设置在沟道区域的上方并与绝缘体绝缘。 还提供了操作存储单元的方法，包括用于将电子从通道中通过绝缘体注入到电荷存储区域上的装置，以及用于将来自注射器的孔穿过阱通过穿过绝缘体的沟槽注入到电荷存储区上的装置。 存储器单元可以在传统的逻辑CMOS工艺中实现。

    Isolation for non-volatile memory cell array
    28.
    发明授权
    Isolation for non-volatile memory cell array 有权
    隔离非易失性存储单元阵列

    公开(公告)号：US08072023B1

    公开(公告)日：2011-12-06

    申请号：US12262599

    申请日：2008-10-31

    Applicant: Chih-Hsin Wang

    Inventor： Chih-Hsin Wang

    IPC: H01L29/788

    CPC classification number: H01L27/11568

    Abstract: A memory device including a plurality of storage regions arranged with storage region intervals. A plurality of conductor lines are juxtaposed the storage region intervals. One or more isolations are provided, each isolation adjacent one or more conductor lines and juxtaposed one or more of the storage regions that are dummy storage regions. The storage regions are charge storage regions in memory cells and each memory cell further includes a first cell region, a second cell region and a cell channel juxtaposed the charge storage region and located between the first cell region and the second cell region. A first array region and a second array region are separated by a first one of the isolations; each array region includes one or more groups of the memory cells where each memory cell includes one of the storage regions.

    Abstract translation: 一种存储装置，包括以存储区域间隔排列的多个存储区域。 多个导线与存储区间隔并列。 提供一个或多个隔离，每个隔离邻近一个或多个导体线并且并置一个或多个作为虚拟存储区域的存储区域。 存储区域是存储单元中的电荷存储区域，并且每个存储单元进一步包括第一单元区域，第二单元区域和单元通道并置电荷存储区域并位于第一单元区域和第二单元区域之间。 第一阵列区域和第二阵列区域被隔离物中的第一个隔离; 每个阵列区域包括一个或多个存储单元组，其中每个存储器单元包括存储区域之一。

    Non-volatile memory cell array and logic
    29.
    发明授权
    Non-volatile memory cell array and logic 有权
    非易失性存储单元阵列和逻辑

    公开(公告)号：US07847374B1

    公开(公告)日：2010-12-07

    申请号：US12168448

    申请日：2008-07-07

    Applicant: Chih-Hsin Wang

    Inventor： Chih-Hsin Wang

    IPC: H01L29/73

    CPC classification number: H01L27/24 ,  H01L27/1026

    Abstract: A semiconductor device comprising a memory region including one or more transistor string arrays, a logic region including one or more logic transistors and an isolation region for isolating the logic transistors. The string array includes a plurality, T, of bipolar junction transistors. The string array includes a common collector region for the T bipolar junction transistors, a common base region for the T bipolar junction transistors, a plurality of emitters, one emitter for each of the T bipolar junction transistors, a number, B, of base contacts for the T bipolar junction transistors where the base contacts electrically couple the common base region and where the number of base contacts, B, is less than the number of transistors, T.

    Abstract translation: 一种半导体器件，包括包括一个或多个晶体管串阵列的存储区域，包括一个或多个逻辑晶体管的逻辑区域和用于隔离逻辑晶体管的隔离区域。 串阵列包括多个T型双极结型晶体管。 串阵列包括用于T双极结晶体管的公共集电极区域，用于T双极结晶体管的公共基极区域，多个发射极，每个T双极结晶体管的一个发射极，基极触点的数量B 对于其中基极接触电耦合公共基极区域并且其中基极触点数B小于晶体管数量T的T双极结晶体管。

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