公开(公告)号：US09184287B2

公开(公告)日：2015-11-10

申请号：US13741157

申请日：2013-01-14

Applicant: Broadcom Corporation

Inventor： Akira Ito

IPC: H01L29/78 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/06 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/1083 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823456 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/495 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7833 ,  H01L29/7848

Abstract: A native p-type metal oxide semiconductor (PMOS) device that exhibits a low threshold voltage and a high drive current over a varying range of short channel lengths and a method for fabricating the same is discussed in the present disclosure. The source and drain regions of the native PMOS device, each include a strained region, a heavily doped raised region, and a lightly doped region. The gate region includes a stacked layer of a gate oxide having a high-k dielectric material, a metal, and a contact metal. The high drive current of the native PMOS device is primarily influenced by the increased carrier mobility due to the strained regions, the lower drain resistance due to the raised regions, and the higher gate capacitance due to the high-k gate oxide of the native PMOS device.

Abstract translation: 在本公开中讨论了在短沟道长度的变化范围内呈现低阈值电压和高驱动电流的天然p型金属氧化物半导体（PMOS）器件及其制造方法。 天然PMOS器件的源极和漏极区域各自包括应变区域，重掺杂凸起区域和轻掺杂区域。 栅极区域包括具有高k介电材料，金属和接触金属的栅极氧化物的堆叠层。 天然PMOS器件的高驱动电流主要受到由于应变区域增加的载流子迁移率的影响，由于升高的区域引起的较低的漏极电阻以及由于天然PMOS的高k栅极氧化物导致的较高的栅极电容 设备。

公开(公告)号：US09105724B2

公开(公告)日：2015-08-11

申请号：US14030569

申请日：2013-09-18

Applicant: Broadcom Corporation

Inventor： Akira Ito

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7835 ,  H01L29/785 ,  H01L29/7851

Abstract: A field effect transistor (FET) having one or more fins provides an extended current path as compared to conventional finFETs. A raised source terminal is disposed on a fin adjacent to a sidewall spacer of a gate structure. The drain terminal and a first portion of the gate structure overlie a first well of a first conductivity type. A raised drain terminal is disposed such that it is spaced apart from the gate structure sidewalls. In some embodiments the drain terminal is disposed on a second, separate fin. the drain terminal and a second portion of the gate structure overlie a second well of a second conductivity type.

Abstract translation: 具有一个或多个鳍片的场效应晶体管（FET）与传统的鳍状FET相比提供了扩展的电流路径。 凸起的源极端子设置在与栅极结构的侧壁间隔物相邻的翅片上。 漏极端子和栅极结构的第一部分覆盖第一导电类型的第一阱。 升高的漏极端子被设置成使其与栅极结构侧壁间隔开。 在一些实施例中，漏极端子设置在第二分开的鳍片上。 漏极端子和栅极结构的第二部分覆盖第二导电类型的第二阱。

公开(公告)号：US08987793B2

公开(公告)日：2015-03-24

申请号：US13898414

申请日：2013-05-20

Applicant: Broadcom Corporation

Inventor： Akira Ito

IPC: H01L29/76 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/7856

Abstract: A semiconductor device based on split multi-gate field-effect transistor radio frequency devices is provided. The semiconductor device includes a substrate and a gate structure above the substrate and orthogonal to a channel axis. The semiconductor device also includes a semiconductor fin structure above the substrate along the channel axis. The semiconductor also includes a gate oxide region beneath the gate structure and in contact with the gate structure and the semiconductor fin structure. The gate oxide region has a first region with a first thickness and a first length. The gate oxide region also has a second region with a second thickness and a second length. The first thickness is greater than the second thickness. The first region and the second region are formed side-by-side along the channel axis.

Abstract translation: 提供了一种基于分离多栅极场效应晶体管射频器件的半导体器件。 半导体器件包括衬底和位于衬底上方并与通道轴线正交的栅极结构。 半导体器件还包括沿着沟道轴线在衬底上方的半导体鳍结构。 半导体还包括栅极结构下方的栅极氧化物区域，并与栅极结构和半导体鳍片结构接触。 栅极氧化物区域具有第一厚度和第一长度的第一区域。 栅极氧化物区域还具有第二厚度和第二长度的第二区域。 第一厚度大于第二厚度。 第一区域和第二区域沿通道轴线并排地形成。

公开(公告)号：US08932912B2

公开(公告)日：2015-01-13

申请号：US13945535

申请日：2013-07-18

Applicant: Broadcom Corporation

Inventor： Akira Ito ,  Xiangdong Chen

IPC: H01L21/82 ,  H01L29/78 ,  H01L27/112 ,  H01L23/525 ,  H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/7816 ,  H01L21/76224 ,  H01L23/5252 ,  H01L27/088 ,  H01L27/11206 ,  H01L27/11226 ,  H01L27/1124 ,  H01L27/11246 ,  H01L27/11266 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66681 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to one embodiment, a one-time programmable (OTP) device having a lateral diffused metal-oxide-semiconductor (LDMOS) structure comprises a pass gate including a pass gate electrode and a pass gate dielectric, and a programming gate including a programming gate electrode and a programming gate dielectric. The programming gate is spaced from the pass gate by a drain extension region of the LDMOS structure. The LDMOS structure provides protection for the pass gate when a programming voltage for rupturing the programming gate dielectric is applied to the programming gate electrode. A method for producing such an OTP device comprises forming a drain extension region, fabricating a pass gate over a first portion of the drain extension region, and fabricating a programming gate over a second portion of the drain extension region.

Abstract translation: 根据一个实施例，具有横向扩散的金属氧化物半导体（LDMOS）结构的一次性可编程（OTP）器件包括包括通过栅电极和通过栅极电介质的通过栅极，以及包括编程门 电极和编程栅极电介质。 编程门通过LDMOS结构的漏极扩展区与通过栅极间隔开。 当用于将编程栅极电介质破裂的编程电压施加到编程栅电极时，LDMOS结构为通路提供保护。 一种用于制造这种OTP器件的方法包括形成漏极延伸区域，在漏极延伸区域的第一部分上制造栅极通孔，以及在漏极延伸区域的第二部分上制造编程栅极。

公开(公告)号：US20170373074A1

公开(公告)日：2017-12-28

申请号：US15208418

申请日：2016-07-12

Applicant: BROADCOM CORPORATION

Inventor： Qing Liu ,  Akira Ito

IPC: H01L27/112 ,  H01L29/161 ,  H01L29/08 ,  H01L29/06 ,  H01L27/12 ,  H01L23/528 ,  H01L23/525 ,  H01L29/51 ,  H01L21/84

CPC classification number: H01L27/11206 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/161 ,  H01L29/517 ,  H01L29/7848

Abstract: A programmable cell includes a semiconductor-on-insulator substrate, a program gate, and a word line gate. The semiconductor-on-insulator substrate includes a semiconductor layer. The semiconductor layer includes a first doped source/drain region, a second doped source/drain region and a region comprising germanium. The program gate is disposed above the region comprising germanium and includes a first gate dielectric layer disposed below a gate conductor. The word line gate is disposed between the first doped source/drain region and the second doped source/drain region.

公开(公告)号：US20160276355A1

公开(公告)日：2016-09-22

申请号：US14692552

申请日：2015-04-21

Applicant: BROADCOM CORPORATION

Inventor： Qintao Zhang ,  Akira Ito

IPC: H01L27/112 ,  H01L21/28 ,  H01L21/265 ,  H01L21/311 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L23/525 ,  H01L21/3115

CPC classification number: H01L27/11206 ,  G11C17/146 ,  H01L21/26586 ,  H01L21/28158 ,  H01L21/31111 ,  H01L21/31155 ,  H01L23/5252 ,  H01L29/42368 ,  H01L29/66795 ,  H01L29/7851

Abstract: A programmable cell includes a split gate structure. The split gate structure includes a thin gate dielectric region and a thick gate dielectric region disposed below a gate conductor. A thickness of the thick oxide region is more than a thickness of the thin oxide region. The programmable cell can be fabricated using angle doping to dope an area associated with the thin dielectric region.

Abstract translation: 可编程单元包括分离栅结构。 分离栅极结构包括薄栅极电介质区域和设置在栅极导体下方的厚栅极电介质区域。 厚氧化物区域的厚度大于薄氧化物区域的厚度。 可以使用角度掺杂来制造可编程单元以掺杂与薄介电区域相关联的区域。

公开(公告)号：US20160211367A1

公开(公告)日：2016-07-21

申请号：US14625047

申请日：2015-02-18

Applicant: Broadcom Corporation

Inventor： Akira Ito ,  Shom Ponoth

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/08 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7824 ,  H01L21/76283 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0865 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/0886 ,  H01L29/1095 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/78624

Abstract: A semiconductor device includes a first well that is disposed in a semiconductor substrate. The semiconductor device further includes a second well that is disposed in the semiconductor substrate. The semiconductor device further includes a source region, a drain region, and a gate structure between the source region and the drain region. The gate structure is disposed above the first well. The source region includes a first conducting contact above the first well and. The drain region includes a second conducting contact above the second well, the drain region being connected with the second well at least partially through a first epi region. The first epi region and the second well are configured to lower a first driving voltage applied on the source region and the drain region to a second voltage applied on the gate structure.

Abstract translation: 半导体器件包括设置在半导体衬底中的第一阱。 半导体器件还包括设置在半导体衬底中的第二阱。 半导体器件还包括在源极区域和漏极区域之间的源极区域，漏极区域和栅极结构。 栅极结构设置在第一阱的上方。 源极区包括在第一阱上方的第一导电接触。 漏极区域包括在第二阱上方的第二导电接触，漏极区域至少部分地通过第一外延区域与第二阱连接。 第一外延区域和第二阱被配置为将施加在源极区域和漏极区域上的第一驱动电压降低到施加在栅极结构上的第二电压。

公开(公告)号：US09337188B2

公开(公告)日：2016-05-10

申请号：US14072723

申请日：2013-11-05

Applicant: Broadcom Corporation

Inventor： Shom Surendran Ponoth ,  Changyok Park ,  Guang-Jye Shiau ,  Akira Ito

IPC: H01L49/02 ,  H01L27/08 ,  H01L27/108 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L27/0629 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/10855 ,  H01L28/40 ,  H01L28/60 ,  H01L28/90 ,  H01L29/0649 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor structure in a semiconductor device includes a semiconductor substrate having a top surface and a bottom surface opposite the top surface, an isolation region having a top surface and a bottom surface, opposite the top surface, the bottom surface of the isolation region being disposed on the top surface of the semiconductor substrate. The capacitor structure also includes a gate terminal structure disposed on the top surface of the isolation region and a diffusion contact structure disposed on the top surface of the isolation region and arranged parallel to the gate terminal structure. In some aspects, the gate terminal structure is connected to a first contact node and the diffusion contact structure is connected to a second contact node, in which the first and second contact nodes form opposing nodes of the capacitor structure.

Abstract translation: 半导体器件中的电容器结构包括具有顶表面和与顶表面相对的底表面的半导体衬底，隔离区域具有与顶表面相对的顶表面和底表面，隔离区域的底表面设置 在半导体衬底的顶表面上。 电容器结构还包括设置在隔离区域的顶表面上的栅极端子结构和设置在隔离区域的顶表面上且平行于栅极端子结构设置的扩散接触结构。 在一些方面，栅极端子结构连接到第一接触节点，并且扩散接触结构连接到第二接触节点，其中第一和第二接触节点形成电容器结构的相对节点。

公开(公告)号：US09165936B2

公开(公告)日：2015-10-20

申请号：US14173744

申请日：2014-02-05

Applicant: BROADCOM CORPORATION

Inventor： Shom Surendran Ponoth ,  Akira Ito ,  Changyok Park

IPC: H01L29/00 ,  H01L27/112 ,  H01L29/78 ,  H01L29/66 ,  H01L23/525

CPC classification number: H01L27/11206 ,  G11C17/16 ,  H01L23/5252 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An anti-fuse device for fin field-effect transistor (finFET) technology includes a dummy gate, an electrically conductive contact, and a diffusion contact. The dummy gate is formed over an end-corner of a fin. The electrically conductive contact is disposed on a portion of the dummy gate and can be used as a first electrode of the device. The diffusion contact is disposed over the fin and can be used as a second electrode of the device.

Abstract translation: 用于鳍状场效应晶体管（finFET）技术的反熔丝器件包括虚拟栅极，导电触点和扩散接触。 虚拟门形成在翅片的端角上。 导电触点设置在虚拟栅极的一部分上，并且可以用作该器件的第一电极。 扩散接触件设置在翅片上并且可以用作该器件的第二电极。

公开(公告)号：US09059280B2

公开(公告)日：2015-06-16

申请号：US13737682

申请日：2013-01-09

Applicant: Broadcom Corporation

Inventor： Akira Ito

IPC: H01L29/78 ,  H01L29/66

Abstract: A semiconductor device includes a first well and a second well implanted in a semiconductor substrate. The semiconductor device further includes a gate structure above the first and second wells between a raised source structure and a raised drain structure. The raised source structure above is in contact with the first well and connected with the gate structure through a first semiconductor fin structure. The raised drain structure above and in contact with the second well and connected with a second semiconductor fin structure. The second semiconductor fin structure includes at least a gap and a lightly doped portion.