公开(公告)号：US20120322265A1

公开(公告)日：2012-12-20

申请号：US13162776

申请日：2011-06-17

Applicant: Chun-Wei HSU ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

Inventor： Chun-Wei HSU ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

IPC: H01L21/304 ,  H01L21/306

CPC classification number: H01L21/31053 ,  H01L21/02065 ,  H01L29/517 ,  H01L29/66545

Abstract: A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.

Abstract translation: 多孔抛光工艺包括以下步骤。 提供半成品半导体元件。 半成品半导体部件包括基板，设置在基板上的栅极和设置在基板上并覆盖栅极的电介质层。 将第一抛光工艺施加到电介质层上。 第二次抛光工艺应用于浇口。 第二抛光工艺利用包含水溶性聚合物表面活性剂，碱性化合物和水的润湿溶液。 多孔抛光工艺可有效去除化学机械抛光中形成的氧化物残留物，从而提高集成电路的性能，降低集成电路的生产成本。

公开(公告)号：US20120264302A1

公开(公告)日：2012-10-18

申请号：US13085502

申请日：2011-04-13

Applicant: Chun-Wei Hsu ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Po-Cheng Huang ,  Chia-Hsi Chen ,  Yen-Ming Chen ,  Chih-Hsun Lin

Inventor： Chun-Wei Hsu ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Po-Cheng Huang ,  Chia-Hsi Chen ,  Yen-Ming Chen ,  Chih-Hsun Lin

IPC: H01L21/306

CPC classification number: H01L21/31053 ,  H01L21/02065 ,  H01L21/76224 ,  H01L29/66545

Abstract: A chemical mechanical polishing (CMP) process includes steps of providing a substrate, performing a first polishing step to the substrate with an acidic slurry, and performing a second polishing step to the substrate with a basic slurry after the first polishing step.

Abstract translation: 化学机械抛光（CMP）工艺包括以下步骤：提供基材，用酸性浆料对基材进行第一抛光步骤，以及在第一抛光步骤之后用碱性浆料对基材进行第二抛光步骤。

公开(公告)号：US20110039408A1

公开(公告)日：2011-02-17

申请号：US12913142

申请日：2010-10-27

Applicant: Kuan-Chi Tsai ,  Chih-Hsun Lin ,  Sheng-Wen Su ,  Shaw-Jang Liou

Inventor： Kuan-Chi Tsai ,  Chih-Hsun Lin ,  Sheng-Wen Su ,  Shaw-Jang Liou

IPC: H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/76808 ,  H01L21/76831

Abstract: Semiconductor devices and methods for fabricating the same. The devices includes a substrate, a first etch stop layer, a dielectric layer, an opening, and an anti-diffusion layer. The first etch stop layer overlies the substrate. The dielectric layer overlies the first etch stop layer. The opening extends through the dielectric layer and the first etch stop layer, and exposes parts of the substrate. The anti-diffusion layer overlies at least sidewalls of the opening, preventing contamination molecule diffusion from at least the first etch stop layer, wherein the anti-diffusion layer is respectively denser than the first etch stop layer and the dielectric layer.

Abstract translation: 半导体器件及其制造方法。 这些器件包括衬底，第一蚀刻停止层，电介质层，开口和反扩散层。 第一蚀刻停止层覆盖在基底上。 介电层覆盖在第一蚀刻停止层上。 开口延伸穿过介电层和第一蚀刻停止层，并露出基板的一部分。 抗扩散层至少覆盖开口的侧壁，防止污染分子从至少第一蚀刻停止层扩散，其中抗扩散层分别比第一蚀刻停止层和电介质层更致密。

公开(公告)号：US10043653B2

公开(公告)日：2018-08-07

申请号：US13595787

申请日：2012-08-27

Applicant: Wei-Cheng Chen ,  Ling-Sung Wang ,  Chih-Hsun Lin ,  Tzu kai Lin

Inventor： Wei-Cheng Chen ,  Ling-Sung Wang ,  Chih-Hsun Lin ,  Tzu kai Lin

IPC: B08B3/02 ,  H01L21/02 ,  H01L21/67 ,  C11D11/00 ,  C11D7/26

CPC classification number: H01L21/02052 ,  C11D7/261 ,  C11D11/0047 ,  H01L21/67028

Abstract: A method of cleaning and drying a semiconductor wafer including inserting a semiconductor wafer into a chamber of a cleaning tool, spinning the semiconductor wafer in a range of about 300 revolutions per minute to about 1600 revolutions per minute, and simultaneously spraying the semiconductor wafer with de-ionized water and a mixture of isopropyl alcohol and nitrogen.

公开(公告)号：US08994097B2

公开(公告)日：2015-03-31

申请号：US13415611

申请日：2012-03-08

Applicant: Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Ching-Hua Chu ,  Ling-Sung Wang

Inventor： Mei-Hsuan Lin ,  Chih-Hsun Lin ,  Ching-Hua Chu ,  Ling-Sung Wang

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66507 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02694 ,  H01L21/30604 ,  H01L21/308 ,  H01L29/165 ,  H01L29/41758 ,  H01L29/45 ,  H01L29/66553 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A device includes a semiconductor substrate, a gate stack over the semiconductor substrate, and a stressor region having at least a portion in the semiconductor substrate and adjacent to the gate stack. The stressor region includes a first stressor region having a first p-type impurity concentration, a second stressor region over the first stressor region, wherein the second stressor region has a second p-type impurity concentration, and a third stressor region over the second stressor region. The third stressor region has a third p-type impurity concentration. The second p-type impurity concentration is lower than the first and the third p-type impurity concentrations.

Abstract translation: 一种器件包括半导体衬底，半导体衬底上的栅极叠层以及具有至少一部分在半导体衬底中并与栅叠层相邻的应力区。 所述应激源区域包括具有第一p型杂质浓度的第一应激源区域，超过所述第一应激区域的第二应激区域，其中所述第二应激区域具有第二p型杂质浓度，以及所述第二应激源上的第三应力区域 地区。 第三应力区域具有第三p型杂质浓度。 第二种p型杂质浓度低于第一和第三种p型杂质浓度。

公开(公告)号：US08879268B2

公开(公告)日：2014-11-04

申请号：US13371497

申请日：2012-02-13

Applicant: Shih-Chang Lee ,  Chi-Hao Jin ,  Ming-Lee Chu ,  Chih-Hsun Lin

Inventor： Shih-Chang Lee ,  Chi-Hao Jin ,  Ming-Lee Chu ,  Chih-Hsun Lin

IPC: H05K7/20

CPC classification number: H05K7/20709 ,  H05K7/2039 ,  H05K7/20409 ,  H05K7/20445 ,  H05K7/20545

Abstract: The present invention discloses a cooling system for an electronic rack, comprising: an electronic rack comprising at least one side wall; at least one electronic chassis comprising a top wall and at least one side wall and disposed inside the electronic rack for housing at least one modular electronics equipment comprising a plurality of electronic components and at least one stationary thermal interface arranged above the plurality of electronic components; a first detachable thermal interface arranged between the top wall of the at least one electronic chassis and the at least one modular electronic equipment; and at least one second detachable thermal interface arranged between the at least one side wall of the electronic rack and the at least one side wall of the at least one electronic chassis.

Abstract translation: 本发明公开了一种电子机架的冷却系统，包括：电子机架，包括至少一个侧壁; 至少一个电子底盘，其包括顶壁和至少一个侧壁并且设置在所述电子机架内部，用于容纳包括多个电子部件和布置在所述多个电子部件上方的至少一个固定热接口的至少一个模块化电子设备; 布置在所述至少一个电子底盘的顶壁和所述至少一个模块化电子设备之间的第一可拆卸热接口; 以及布置在所述电子机架的所述至少一个侧壁与所述至少一个电子底盘的所述至少一个侧壁之间的至少一个第二可拆卸热接口。

公开(公告)号：US08779526B2

公开(公告)日：2014-07-15

申请号：US13283603

申请日：2011-10-28

Applicant: Chun-Wei Hsu ,  Po-Cheng Huang ,  Ren-Peng Huang ,  Jie-Ning Yang ,  Chia-Lin Hsu ,  Teng-Chun Tsai ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Yen-Ming Chen ,  Yu-Ting Li

Inventor： Chun-Wei Hsu ,  Po-Cheng Huang ,  Ren-Peng Huang ,  Jie-Ning Yang ,  Chia-Lin Hsu ,  Teng-Chun Tsai ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Yen-Ming Chen ,  Yu-Ting Li

IPC: H01L29/78

CPC classification number: H01L27/0629

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation (STI) on the substrate of the resistor region; forming a tank in the STI of the resistor region; and forming a resistor in the tank and on the surface of the STI adjacent to two sides of the tank.

Abstract translation: 公开了半导体器件的制造方法。 该方法包括以下步骤：提供具有晶体管区域和电阻器区域的衬底; 在电阻器区域的衬底上形成浅沟槽隔离（STI）; 在电阻区域的STI中形成槽; 并且在罐中形成电阻器，并且在与槽的两侧相邻的STI的表面上形成电阻器。

公开(公告)号：US20140053869A1

公开(公告)日：2014-02-27

申请号：US13595787

申请日：2012-08-27

Applicant: Wei-Cheng Chen ,  Ling-Sung Wang ,  Chih-Hsun Lin ,  Tzu kai Lin

Inventor： Wei-Cheng Chen ,  Ling-Sung Wang ,  Chih-Hsun Lin ,  Tzu kai Lin

IPC: B08B3/02 ,  H01L21/02

CPC classification number: H01L21/02052 ,  C11D7/261 ,  C11D11/0047 ,  H01L21/67028

Abstract: A method of cleaning and drying a semiconductor wafer including inserting a semiconductor wafer into a chamber of a cleaning tool, spinning the semiconductor wafer in a range of about 300 revolutions per minute to about 1600 revolutions per minute, and simultaneously spraying the semiconductor wafer with de-ionized water and a mixture of isopropyl alcohol and nitrogen.

Abstract translation: 一种清洁和干燥半导体晶片的方法，包括将半导体晶片插入清洁工具的腔室中，将半导体晶片在约300转/分钟至约1600转/分钟的范围内旋转，同时用de 去离子水和异丙醇和氮气的混合物。

公开(公告)号：US08513128B2

公开(公告)日：2013-08-20

申请号：US13162776

申请日：2011-06-17

Applicant: Chun-Wei Hsu ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

Inventor： Chun-Wei Hsu ,  Po-Cheng Huang ,  Teng-Chun Tsai ,  Chia-Lin Hsu ,  Chih-Hsun Lin ,  Chang-Hung Kung ,  Chia-His Chen ,  Yen-Ming Chen

IPC: H01L21/304 ,  H01L21/306 ,  B44C1/22

CPC classification number: H01L21/31053 ,  H01L21/02065 ,  H01L29/517 ,  H01L29/66545

Abstract: A poly opening polish process includes the following steps. A semi-finished semiconductor component is provided. The semi-finished semiconductor component includes a substrate, a gate disposed on the substrate, and a dielectric layer disposed on the substrate and covering the gate. A first polishing process is applied onto the dielectric layer. A second polishing process is applied to the gate. The second polishing process utilizes a wetting solution including a water soluble polymer surfactant, an alkaline compound and water. The poly opening polish process can effectively remove an oxide residue formed in the chemical mechanical polish, thereby improving the performance of the integrated circuit and reducing the production cost of the integrated circuit.

Abstract translation: 多孔抛光工艺包括以下步骤。 提供半成品半导体元件。 半成品半导体部件包括基板，设置在基板上的栅极和设置在基板上并覆盖栅极的电介质层。 将第一抛光工艺施加到电介质层上。 第二次抛光工艺应用于浇口。 第二抛光工艺利用包含水溶性聚合物表面活性剂，碱性化合物和水的润湿溶液。 多孔抛光工艺可有效去除化学机械抛光中形成的氧化物残留物，从而提高集成电路的性能，降低集成电路的生产成本。

公开(公告)号：US20130069162A1

公开(公告)日：2013-03-21

申请号：US13233453

申请日：2011-09-15

Applicant: Mei-Hsuan Lin ,  Chih-Chan Lu ,  Chih-Hsun Lin ,  Chih-Kang Chao ,  Ling-Sung Wang ,  Jen-Pan Wang

Inventor： Mei-Hsuan Lin ,  Chih-Chan Lu ,  Chih-Hsun Lin ,  Chih-Kang Chao ,  Ling-Sung Wang ,  Jen-Pan Wang

IPC: H01L27/088 ,  G06F17/50

CPC classification number: G06F17/50 ,  G06F17/5072 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823475 ,  H01L21/823481 ,  H01L25/00 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/12 ,  H01L29/788 ,  H01L2924/0002 ,  H03K19/00 ,  H01L2924/00

Abstract: The present disclosure provides an integrated circuit design method. In an example, a method includes receiving an integrated circuit design layout that includes an active region feature, a contact feature, and an isolation feature, wherein a portion of the active region feature is disposed between the contact feature and the isolation feature; determining whether a thickness of the portion of the active region feature disposed between the contact feature and the isolation feature is less than a threshold value; and modifying the integrated circuit design layout if the thickness is less than the threshold value, wherein the modifying includes adding a supplementary active region feature adjacent to the portion of the active region feature disposed between the contact feature and the isolation feature.

Abstract translation: 本公开提供了一种集成电路设计方法。 在一个示例中，一种方法包括接收包括有源区域特征，接触特征和隔离特征的集成电路设计布局，其中有源区域特征的一部分设置在接触特征和隔离特征之间; 确定布置在接触特征和隔离特征之间的有源区域特征的部分的厚度是否小于阈值; 以及如果所述厚度小于所述阈值，则修改所述集成电路设计布局，其中所述修改包括在所述接触特征与所述隔离特征之间的所述有源区域特征的所述部分附近添加辅助有源区域特征。