公开(公告)号：US09978430B2

公开(公告)日：2018-05-22

申请号：US13733884

申请日：2013-01-03

申请人： Eun-Sung Seo ,  Chul-Woo Park ,  Hong-Sun Hwang

发明人： Eun-Sung Seo ,  Chul-Woo Park ,  Hong-Sun Hwang

IPC分类号： G11C7/00 ,  G11C11/406

CPC分类号： G11C7/00 ,  G11C11/40611

摘要： A memory system includes at least one memory device and a memory controller. The at least one memory device includes a refresh request circuit that generates refresh request signals at timings based on data retention times of memory cells, such as based on individual data retention times of a memory cell row. The memory controller schedules operation commands for the at least one memory device in response to the received refresh request signals.

公开(公告)号：US09070465B2

公开(公告)日：2015-06-30

申请号：US13586973

申请日：2012-08-16

申请人： Jong-Pil Son ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hyun-Ho Choi

发明人： Jong-Pil Son ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hyun-Ho Choi

IPC分类号： G11C11/00 ,  G11C11/16

CPC分类号： G11C11/161 ,  G11C11/1659 ,  G11C11/1673

摘要： An anti-fuse circuit includes an array of anti-fuses. Each anti-fuse has a tunneling magneto-resistance (TMR) element series connected with a transistor, such that breakdown of a magnetic tunnel junction (MTJ) in response to an applied first voltage stores fuse information. A sensing circuit senses and amplifies respective output signals provided by the anti-fuses.

摘要翻译： 反熔丝电路包括一组抗熔丝。 每个反熔丝具有与晶体管连接的隧道磁阻（TMR）元件串联，使得响应于施加的第一电压的磁隧道结（MTJ）的击穿存储熔丝信息。 感测电路感测并放大由防熔丝提供的各自的输出信号。

公开(公告)号：US08553484B2

公开(公告)日：2013-10-08

申请号：US13238553

申请日：2011-09-21

申请人： Sua Kim ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hak-Soo Yu

发明人： Sua Kim ,  Chul-Woo Park ,  Hong-Sun Hwang ,  Hak-Soo Yu

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C11/4099

摘要： A semiconductor memory device includes a memory cell and a first reference memory cell. The memory cell includes a first switching element and a first capacitor for storing data. The first switching element is controlled by a first wordline, and has a first terminal connected to a first terminal of the first capacitor and a second terminal connected to a first bitline. The first capacitor has a second terminal for receiving a first plate voltage. The first reference memory cell includes a first reference switching element and a first capacitor. The first switching element is controlled by a first reference wordline, and has a first terminal connected to a first terminal of the first reference capacitor and a second terminal connected to a second bitline. The first reference capacitor has a second terminal receiving a first reference plate voltage different from the first plate voltage.

摘要翻译： 半导体存储器件包括存储单元和第一参考存储单元。 存储单元包括第一开关元件和用于存储数据的第一电容器。 第一开关元件由第一字线控制，并且具有连接到第一电容器的第一端子的第一端子和连接到第一位线的第二端子。 第一电容器具有用于接收第一板电压的第二端子。 第一参考存储单元包括第一参考开关元件和第一电容器。 第一开关元件由第一参考字线控制，并且具有连接到第一参考电容器的第一端子的第一端子和连接到第二位线的第二端子。 第一参考电容器具有接收与第一板电压不同的第一参考板电压的第二端子。

公开(公告)号：US20120212989A1

公开(公告)日：2012-08-23

申请号：US13304851

申请日：2011-11-28

申请人： Hak-Soo YU ,  Su-A Kim ,  Hong-Sun Hwang ,  Chul-Woo Park

发明人： Hak-Soo YU ,  Su-A Kim ,  Hong-Sun Hwang ,  Chul-Woo Park

IPC分类号： G11C5/02

CPC分类号： G11C7/02 ,  G11C7/062 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10897

摘要： A semiconductor memory device is disclosed. The semiconductor memory device includes a memory array block, a first word line and a second word line. The memory array block includes a plurality of adjacent columns of memory cells, each column of memory cells including a plurality of consecutive memory cells having a plurality of respective consecutive cell transistors that comprise at least a first group of cell transistors and a second group of cell transistors. The first word line is disposed above the plurality of respective consecutive cell transistors and electrically connected to the first group of cell transistors, and the second word line is disposed below the plurality of respective consecutive cell transistors and electrically connected to the second group of cell transistors.

摘要翻译： 公开了一种半导体存储器件。 半导体存储器件包括存储器阵列块，第一字线和第二字线。 存储器阵列块包括多个相邻列的存储器单元，每列存储器单元包括多个连续的存储单元，其具有多个相应的连续单元晶体管，其包括至少第一组单元晶体管和第二组单元 晶体管。 第一字线设置在多个相应的连续单元晶体管的上方并电连接到第一组单元晶体管，第二字线设置在多个相应的连续单元晶体管的下方，并电连接到第二组单元晶体管 。

公开(公告)号：US20120210054A1

公开(公告)日：2012-08-16

申请号：US13503511

申请日：2010-10-21

申请人： Chang-Jung Kim ,  In-Kyeong Yoo ,  Ho-Jung Kim ,  Chul-Woo Park

发明人： Chang-Jung Kim ,  In-Kyeong Yoo ,  Ho-Jung Kim ,  Chul-Woo Park

IPC分类号： G06F12/00

CPC分类号： G11B20/00086 ,  G06F12/0246 ,  G06F21/10 ,  G06F21/79 ,  G11B2220/60 ,  G11C7/24

摘要： Provided are a storage medium, which has a security function, for storing media content and an output apparatus for outputting data stored in the storage medium. The storage medium includes a controller for converting at least one of a position of pins of a connector and a storage position of media content in a memory unit in order to control transmission of the media content in the memory unit to the output apparatus.

摘要翻译： 提供了具有用于存储媒体内容的安全功能的存储介质和用于输出存储在存储介质中的数据的输出设备。 存储介质包括控制器，用于将连接器的引脚的位置和存储器单元中的媒体内容的存储位置中的至少一个转换为控制存储器单元中的媒体内容向输出设备的传输。

公开(公告)号：US20100118631A1

公开(公告)日：2010-05-13

申请号：US12591196

申请日：2009-11-12

申请人： Jin-Young Kim ,  Chul-Woo Park ,  Ki-Whan Song

发明人： Jin-Young Kim ,  Chul-Woo Park ,  Ki-Whan Song

IPC分类号： G11C7/00 ,  G11C7/06

CPC分类号： G11C11/4099 ,  G11C11/4091

摘要： A semiconductor memory device having the mismatch cell makes a capacitance difference between a bit line pair relatively large during a read operation using at least one dummy memory cell as a mismatch cell selected together with a corresponding memory cell. Therefore, data of a semiconductor memory device may be detected more easily.

摘要翻译： 具有不匹配单元的半导体存储器件在使用至少一个虚拟存储器单元作为与对应的存储器单元一起选择的不匹配单元的读取操作期间，位线对之间的电容差相对较大。 因此，可以更容易地检测半导体存储器件的数据。

公开(公告)号：US07679589B2

公开(公告)日：2010-03-16

申请号：US11326692

申请日：2006-01-06

申请人： Chul-Woo Park

发明人： Chul-Woo Park

IPC分类号： G09G3/36

CPC分类号： G09G3/3696 ,  G09G3/3648 ,  G09G3/3685 ,  G09G2300/0491 ,  G09G2310/027 ,  G09G2320/0252

摘要： The present invention relates to a liquid crystal display device with a source driver in which a significant signal delay is not generated, and which has a fast response speed. The present invention also provides a liquid crystal display device comprising a scan driver including a D/A converter for outputting analog signals corresponding to gradation data input, a triangular wave generator for outputting triangular wave signals, and a comparator for applying data voltage to each pixel which include OCB liquid crystal cells by comparing the analog signals with the triangular wave signals. The data voltage is a PWM pulse with a varied voltage width.

摘要翻译： 本发明涉及一种具有源极驱动器的液晶显示装置，其中不产生显着的信号延迟，并具有快速的响应速度。 本发明还提供一种液晶显示装置，包括：扫描驱动器，包括用于输出对应于灰度数据输入的模拟信号的D / A转换器，用于输出三角波信号的三角波发生器;以及用于向每个像素施加数据电压的比较器 其通过将模拟信号与三角波信号进行比较来包括OCB液晶单元。 数据电压是具有不同电压宽度的PWM脉冲。

公开(公告)号：US20090273728A1

公开(公告)日：2009-11-05

申请号：US12385972

申请日：2009-04-24

申请人： Young-Woo Song ,  Jong-Hyuk Lee ,  Kyu-Hwan Hwang ,  Jong-Seok Oh ,  Joon-Gu Lee ,  Jae-Heung Ha ,  Chul-Woo Park

发明人： Young-Woo Song ,  Jong-Hyuk Lee ,  Kyu-Hwan Hwang ,  Jong-Seok Oh ,  Joon-Gu Lee ,  Jae-Heung Ha ,  Chul-Woo Park

IPC分类号： G02F1/1335

CPC分类号： G02F1/133536 ,  G02B5/3058 ,  G02F2001/133548 ,  G02F2201/08 ,  G02F2201/38

摘要： A liquid crystal display apparatus includes a backlight unit, a second polarization layer, a liquid crystal layer disposed between the backlight unit and the second polarization layer, a first polarization layer disposed between the backlight unit and the liquid crystal layer. In an embodiment, a surface of the first polarization layer facing the backlight unit includes a reflective surface and a surface of the first polarization layer facing the backlight unit includes an absorbent surface. In another embodiment, the first polarization layer includes grids, which include a metal, and absorbing members, which include dielectric materials. In another embodiment, the first polarization layer includes grids, each of which includes a first component including a dielectric material and a second component including a metal.

摘要翻译： 液晶显示装置包括背光单元，第二偏振层，设置在背光单元和第二偏振层之间的液晶层，设置在背光单元和液晶层之间的第一偏振层。 在一个实施例中，面向背光单元的第一偏振层的表面包括反射表面，并且面向背光单元的第一偏振层的表面包括吸收表面。 在另一个实施例中，第一偏振层包括包括金属的网格和包括电介质材料的吸收构件。 在另一个实施例中，第一偏振层包括格栅，每个栅格包括包括电介质材料的第一元件和包括金属的第二元件。

公开(公告)号：US20080165243A1

公开(公告)日：2008-07-10

申请号：US11854459

申请日：2007-09-12

申请人： Jong-Seok Oh ,  Jong-hyuk Lee ,  Young-Woo Song ,  Kyu-Hwan Hwang ,  Joon-Gu Lee ,  Jae-Heung Ha ,  Chul-Woo Park

发明人： Jong-Seok Oh ,  Jong-hyuk Lee ,  Young-Woo Song ,  Kyu-Hwan Hwang ,  Joon-Gu Lee ,  Jae-Heung Ha ,  Chul-Woo Park

IPC分类号： B41J2/45 ,  H01J1/62

CPC分类号： B41J2/45 ,  H01L51/5203

摘要： A print head includes a light source, a driver chip electrically connected to the light source and a lens array on the side of light irradiation of the light source. The light source includes a substrate and a plurality of organic light emitting diodes arranged in adjacent groups on the substrate. Each of the organic light emitting diodes of a group includes a first electrode, an organic emissive layer, and a second electrode. First wires on the substrate connect each first electrode to a first electrode in an adjacent group. A separator is located between the adjacent groups. A first pad on the substrate is electrically connected to each first electrode of each of the organic light emitting diodes of a first group and a plurality of second pads are located on the substrate, each second pad electrically connected to the second electrode of each group.

摘要翻译： 打印头包括光源，电连接到光源的驱动器芯片和在光源的光照射侧的透镜阵列。 光源包括基板和布置在基板上的相邻组中的多个有机发光二极管。 组中的每个有机发光二极管包括第一电极，有机发光层和第二电极。 基板上的第一导线将每个第一电极连接到相邻组中的第一电极。 分隔物位于相邻组之间。 衬底上的第一焊盘电连接到第一组的每个有机发光二极管的每个第一电极，并且多个第二焊盘位于衬底上，每个第二焊盘电连接到每个组的第二电极。

公开(公告)号：US07259978B2

公开(公告)日：2007-08-21

申请号：US11221684

申请日：2005-09-08

申请人： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

发明人： Chul-Woo Park ,  Jung-Bae Lee ,  Young-Sun Min ,  Jong-Hyun Choi ,  Jong-Eon Lee

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C7/18 ,  G11C8/14

摘要： A semiconductor memory device may include a memory cell array, a bit line sense amplifier, a sub word line driver, and an electrode. The memory cell array may include a sub memory cell array connected between sub word lines and bit line pairs and having memory cells which are selected in response to a signal transmitted to the sub word lines and column selecting signal lines. The bit line sense amplifier may be configures to sense and amplify data of the bit line pairs. The sub word line driver may be configured to combine signals transmitted from word selecting signal lines and signals transmitted from main word lines to select the sub word lines. Moreover, the memory cell array may be configured to transmit data between the bit line pairs and local data line pairs and to transmit data between the local data line pairs and global data line pairs. The electrode may be configured to cover the whole memory cell array and to apply a voltage needed for the memory cells. The local data line pairs may be arranged on a first layer above the electrode in the same direction as the sub word line. The column selecting signal lines and the global data line pairs may be arranged on a second layer above the electrode in the same direction as the bit line. The word selecting signal lines and the main word lines may be arranged on a third layer above the electrode in the same direction as the sub word line. Related methods of signal line arrangement are also discussed.

摘要翻译： 半导体存储器件可以包括存储单元阵列，位线读出放大器，子字线驱动器和电极。 存储单元阵列可以包括连接在子字线和位线对之间并具有响应于发送到子字线和列选择信号线的信号而被选择的存储器单元的子存储单元阵列。 位线读出放大器可以被配置为感测和放大位线对的数据。 子字线驱动器可以被配置为组合从字选择信号线发送的信号和从主字线发送的信号，以选择子字线。 此外，存储单元阵列可以被配置为在位线对和本地数据线对之间传输数据，并且在本地数据线对和全局数据线对之间传送数据。 电极可以被配置为覆盖整个存储单元阵列并施加存储单元所需的电压。 局部数据线对可以以与子字线相同的方向布置在电极上方的第一层上。 列选择信号线和全局数据线对可以以与位线相同的方向布置在电极上方的第二层上。 字选择信号线和主字线可以沿与子字线相同的方向布置在电极上方的第三层上。 还讨论了信号线布置的相关方法。