中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

55 records (took 0.027 seconds)

    CORE PRIORITIZATION FOR HETEROGENEOUS ON-CHIP NETWORKS
    24.
    发明申请
    CORE PRIORITIZATION FOR HETEROGENEOUS ON-CHIP NETWORKS 审中-公开
    异构片上网络的核心优先

    公开(公告)号：US20170046198A1

    公开(公告)日：2017-02-16

    申请号：US15306004

    申请日：2014-04-24

    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

    Inventor： Yan Solihin

    IPC: G06F9/48 ,  G06F1/32

    CPC classification number: G06F9/4818 ,  G06F1/3243 ,  G06F1/3296 ,  G06F9/45558 ,  G06F9/505 ,  G06F2009/45583 ,  Y02D10/152 ,  Y02D10/22 ,  Y02D50/20

    Abstract: A processor may comprise a plurality of cores operating at heterogeneous frequencies communicatively coupled by a network of routers also operating at heterogeneous frequencies. A core may be prioritized for thread execution based on operating frequencies of routers on a path from the core to a memory controller. Relatively higher priority may be assigned to cores having a path comprising only routers operating at a relatively higher frequency. A combined priority for thread execution may be based on core frequency, router frequency, and the frequency of routers on a path from the core to a memory controller. A core may be selected based primarily on core operating frequency when cache misses fall below a threshold value.

    Abstract translation: 处理器可以包括以异构频率操作的多个核心，其通过也以异构频率工作的路由器的网络通信耦合。 基于从核心到存储器控制器的路径上的路由器的操作频率，可以将核心优先于线程执行。 可以将相对较高的优先级分配给具有仅包括以相对较高频率操作的路由的路径的核。 线程执行的组合优先级可以基于核心频率，路由器频率以及从核心到存储器控制器的路径上的路由器的频率。 当高速缓存未命中低于阈值时，可以主要基于核心操作频率来选择核心。

    Detecting Unidirectional Resistance Drift Errors In A Multilevel Cell of a Phase Change Memory
    25.
    发明申请
    Detecting Unidirectional Resistance Drift Errors In A Multilevel Cell of a Phase Change Memory 有权
    检测相变存储器的多电平单元中的单向电阻漂移误差

    公开(公告)号：US20160085617A1

    公开(公告)日：2016-03-24

    申请号：US14492186

    申请日：2014-09-22

    Applicant: Empire Technology Development LLC

    Inventor： Yan Solihin

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/1004 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1072 ,  G11C7/1006 ,  G11C11/5678 ,  G11C29/42 ,  G11C29/52

    Abstract: Technologies are generally described herein to detect unidirectional resistance drift errors in a multilevel cell of a phase change memory. The resistance levels of the multilevel cell of the phase change memory may be encoded to detect unidirectional resistance drift errors. In some examples, Berger Code-compatible encoding may be used. When a word is written to the multilevel cell, a write check code may be generated. The write check code may be a binary representation of the number of zeroes contained in the word as written. When the word is read from the multilevel cell, a read check code may be generated. The read check code may be a binary representation of the number of zeroes contained in the word as read. An error can be detected if a comparison indicates that the write check code and the read check code are different.

    Abstract translation: 这里通常描述技术来检测相变存储器的多电平单元中的单向电阻漂移误差。 可以编码相变存储器的多电平单元的电阻电平以检测单向电阻漂移误差。 在一些示例中，可以使用Berger Code兼容的编码。 当一个单词写入多层单元时，可能会生成一个写检查代码。 写检查码可以是写入的单词中包含的零数的二进制表示。 当从多级单元读取该单词时，可以生成读取校验码。 读取校验码可以是包含在读取的单词中的零数的二进制表示。 如果比较指示写入检查码和读取校验码不同，则可以检测到错误。

    DYNAMIC ROUTER POWER CONTROL IN MULTI-CORE PROCESSORS
    26.
    发明申请
    DYNAMIC ROUTER POWER CONTROL IN MULTI-CORE PROCESSORS 有权
    多核处理器动态路由器功率控制

    公开(公告)号：US20160026227A1

    公开(公告)日：2016-01-28

    申请号：US14337748

    申请日：2014-07-22

    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

    Inventor： MAZEN KHARBUTLI ,  Yan Solihin

    IPC: G06F1/26 ,  G06F1/32

    CPC classification number: G06F1/263 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    Abstract: Technologies are generally described for systems, devices and methods effective to dynamically select at least one power supply rail for a router. In some examples, a power control unit may be configured to determine a buffer occupancy level of one or more buffers of the router. In some further examples, the buffer occupancy level may be compared to a threshold value. In various other examples, the at least one power supply rail of the router may be switched from a first power rail to a second power rail based on the results of the comparison.

    Abstract translation: 技术通常描述为有效动态地为路由器选择至少一个电源轨的系统，设备和方法。 在一些示例中，功率控制单元可以被配置为确定路由器的一个或多个缓冲器的缓冲器占用水平。 在一些其他示例中，可以将缓冲器占用水平与阈值进行比较。 在各种其他示例中，基于比较的结果，路由器的至少一个电源轨可以从第一电力轨道切换到第二电力轨。

    INCREASED REFRESH INTERVAL AND ENERGY EFFICIENCY IN A DRAM
    27.
    发明申请
    INCREASED REFRESH INTERVAL AND ENERGY EFFICIENCY IN A DRAM 有权
    在DRAM中增加了刷新间隔和能源效率

    公开(公告)号：US20150243340A1

    公开(公告)日：2015-08-27

    申请号：US14371180

    申请日：2013-09-01

    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT LLC

    Inventor： Yan Solihin

    IPC: G11C11/4074 ,  G11C7/10 ,  G11C11/406

    CPC classification number: G06F11/004 ,  G11C7/1072 ,  G11C11/40 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4074 ,  G11C29/023 ,  G11C29/028 ,  G11C29/44 ,  G11C29/50016 ,  G11C29/783 ,  G11C2211/4061

    Abstract: Techniques described herein generally include methods and systems related to designing and operating a DRAM device that has significantly reduced refresh energy use. A method for designing a DRAM optimizes or otherwise improves the DRAM for energy efficiency based on a measured or predicted failure probability of memory cells in the DRAM. The DRAM may be configured to operate at an increased refresh interval, thereby reducing DRAM refresh energy but causing a predictable portion of the memory cells in the DRAM to leak electrical energy too quickly to retain data. The DRAM is further configured with a selected a number of spare memory cells for replacing the “leaky” memory cells, so that operation of the DRAM at the increased refresh interval may result in little or no reduction in capacity of the DRAM.

    Abstract translation: 本文描述的技术通常包括与设计和操作具有显着降低的刷新能量使用的DRAM设备相关的方法和系统。 基于DRAM中的存储器单元的测量或预测的故障概率，用于设计DRAM的方法优化或以其他方式改进用于能量效率的DRAM。 DRAM可以被配置为以增加的刷新间隔进行操作，从而减少DRAM刷新能量，但是使DRAM中的存储器单元的可预测部分太快地泄漏电能以保留数据。 DRAM进一步配置有选择的多个备用存储器单元以替换“泄漏”存储单元，使得在增加的刷新间隔的DRAM的操作可能导致DRAM的容量很少或不降低。

    ONE-CACHEABLE MULTI-CORE ARCHITECTURE
    28.
    发明申请
    ONE-CACHEABLE MULTI-CORE ARCHITECTURE 有权
    单速多核架构

    公开(公告)号：US20140237185A1

    公开(公告)日：2014-08-21

    申请号：US13982620

    申请日：2013-02-21

    Applicant: EMPIRE TECHNOLOGY DEVELOPMENT, LLC.

    Inventor： Yan Solihin

    IPC: G06F12/08

    CPC classification number: G06F12/0811 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/1027

    Abstract: Technologies are generally described for methods, systems, and devices effective to implement one-cacheable multi-core architectures. In one example, a multi-core processor that includes a first and second tile may be configured to implement a one-cacheable architecture. The second tile may be configured to generate a request for a data block. The first tile may be configured to receive the request for the data block, and determine that the requested data block is part of a group of data blocks identified as one-cacheable. The first tile may further determine that the requested data block is stored in a first cache in the first tile. The first tile may send the data block from the first cache in the first tile to the second tile, and invalidate the data blocks of the group of data blocks in the first cache in the first tile.

    Abstract translation: 技术通常被描述为有效实现单缓存多核架构的方法，系统和设备。 在一个示例中，包括第一和第二瓦片的多核处理器可以被配置为实现单缓存架构。 第二瓦片可以被配置为产生对数据块的请求。 第一瓦片可以被配置为接收对数据块的请求，并且确定所请求的数据块是被识别为单缓存的一组数据块的一部分。 第一瓦片还可以确定所请求的数据块被存储在第一瓦片中的第一高速缓存中。 第一瓦片可以将数据块从第一瓦片中的第一高速缓存发送到第二瓦片，并使第一瓦片中的第一高速缓存中的数据块组的数据块无效。

    Aggregating Cache Eviction Notifications to a Directory
    29.
    发明申请
    Aggregating Cache Eviction Notifications to a Directory 有权
    将缓存撤销通知集合到目录

    公开(公告)号：US20140229680A1

    公开(公告)日：2014-08-14

    申请号：US13982607

    申请日：2013-02-11

    Applicant: Empire Technology Development LLC

    Inventor： Yan Solihin

    IPC: G06F12/08 ,  G06F12/12

    CPC classification number: G06F12/082 ,  G06F12/0817

    Abstract: Technologies are described herein generally relate to aggregation of cache eviction notifications to a directory. Some example technologies may be utilized to update an aggregation table to reflect evictions of a plurality of blocks from a plurality of block addresses of at least one cache memory. An aggregate message can be generated, where the message specifies the evictions of the plurality of blocks as reflected in the aggregation table. The aggregate message can be sent to the directory. The directory can parse the aggregate message and update a plurality of directory entries to reflect the evictions from the cache memory as specified in the aggregate message.

    Abstract translation: 本文中描述的技术通常涉及将缓存逐出通知集合到目录。 可以使用一些示例性技术来更新聚合表以反映从至少一个高速缓存存储器的多个块地址中的多个块的驱逐。 可以生成聚合消息，其中消息指定聚合表中反映的多个块的逐出。 聚合消息可以发送到目录。 该目录可以解析聚合消息并更新多个目录条目以反映聚合消息中指定的缓存中的驱逐。

Patent Agency Ranking