公开(公告)号：US20140068626A1

公开(公告)日：2014-03-06

申请号：US13993089

申请日：2011-12-30

申请人： Altug Koker ,  Aditya Navale ,  Balaji Vembu ,  Murali Ramadoss

发明人： Altug Koker ,  Aditya Navale ,  Balaji Vembu ,  Murali Ramadoss

IPC分类号： G06F9/50

CPC分类号： G06F9/50 ,  G06F9/4812 ,  G06F9/545 ,  G06F12/1491 ,  G06F15/167

摘要： Transitions to ring 0, each time an application wants to use an adjunct processor, are avoided, saving central processor operating cycles and improving efficiency. Instead, initially each application is registered and setup to use adjunct processor resources in ring 3.

摘要翻译： 每次应用程序想要使用辅助处理器时，转换到0，避免中断处理器运行周期并提高效率。 相反，最初每个应用程序都被注册并设置为在环3中使用辅助处理器资源。

公开(公告)号：US07353349B2

公开(公告)日：2008-04-01

申请号：US11137700

申请日：2005-05-24

申请人： Jonathan B. Sadowsky ,  Aditya Navale

发明人： Jonathan B. Sadowsky ,  Aditya Navale

IPC分类号： G06F12/00

CPC分类号： G06F12/0859 ,  G06F12/0215

摘要： A method and apparatus for reordering memory requests for page coherency. Various data streams are frequently found in separate areas of physical memory (i.e. each data stream is found in a separate memory “page”). Because these requests from different streams become intermixed, a certain amount of latency results from the resulting page “breaks.” These page breaks occur when consecutive requests are from different data streams, requiring accesses to different memory pages. When several separate streams of data are requested by a client, page coherency between requests diminishes. A reordering device regains lost page coherency, thereby reducing the amount of latency and increasing overall system performance.

摘要翻译： 一种用于重新排序页面一致性的存储器请求的方法和装置。 经常在物理存储器的不同区域中找到各种数据流（即，每个数据流在单独的存储器“页面”中找到）。 因为来自不同流的这些请求被混合，所以产生的页面“断点”会导致一定量的延迟。 当连续的请求来自不同的数据流，需要访问不同的内存页时，会出现这些分页符。 当客户端请求几个单独的数据流时，请求之间的页面一致性减少。 重新排序设备恢复丢失页面一致性，从而减少延迟量并提高整体系统性能。

公开(公告)号：US09916257B2

公开(公告)日：2018-03-13

申请号：US13191327

申请日：2011-07-26

申请人： Rajesh M. Sankaran ,  Altug Koker ,  Philip R. Lantz ,  Asit K. Mallick ,  James B. Crossland ,  Aditya Navale ,  Gilbert Neiger ,  Andrew V. Anderson

发明人： Rajesh M. Sankaran ,  Altug Koker ,  Philip R. Lantz ,  Asit K. Mallick ,  James B. Crossland ,  Aditya Navale ,  Gilbert Neiger ,  Andrew V. Anderson

IPC分类号： G06F12/10 ,  G06F12/1027 ,  G06F12/1081

CPC分类号： G06F12/1027 ,  G06F12/1081 ,  G06F2212/1016 ,  G06F2212/1048 ,  G06F2212/303 ,  G06F2212/682 ,  G06F2212/683

摘要： Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

公开(公告)号：US09659342B2

公开(公告)日：2017-05-23

申请号：US13931915

申请日：2013-06-29

申请人： Hema Chand Nalluri ,  Aditya Navale ,  Murali Ramadoss ,  Jeffery S. Boles

发明人： Hema Chand Nalluri ,  Aditya Navale ,  Murali Ramadoss ,  Jeffery S. Boles

IPC分类号： G06F9/48 ,  G06T1/60 ,  G06T1/20

CPC分类号： G06T1/60 ,  G06F9/48 ,  G06F9/485 ,  G06T1/20

摘要： Mid-command buffer preemption is described for graphics workloads in a graphics processing environment. In one example, instructions of a first context are executed at a graphics processor, the first context has a sequence of instructions in an addressable buffer and at least one of the instructions is a preemption instruction. Upon executing the preemption instruction, execution of the first context is stopped before the sequence of instructions is completed. An address is stored for an instruction with which the first context will be resumed. The second context is executed, and upon completion of the execution of the second context, the execution of the first context is resumed at the stored address.

公开(公告)号：US09268691B2

公开(公告)日：2016-02-23

申请号：US13993680

申请日：2012-06-11

申请人： Saurabh Sharma ,  Altug Koker ,  Aditya Navale

发明人： Saurabh Sharma ,  Altug Koker ,  Aditya Navale

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34 ,  G06F12/06

CPC分类号： G06F12/0607 ,  G06F2212/302

摘要： A mechanism implemented by a controller enables efficient access to an interleaved memory system that includes M modules, M being (2n+1) or (2n−1), n being a positive integer number. Upon receiving an address N, the controller performs shift and add/subtract operations to obtain a quotient of N divided by M based on a binomial series expansion of N over M. The controller computes a remainder of N divided by M based on the quotient. The controller then accesses one of the modules in the memory based on the remainder.

摘要翻译： 由控制器实现的机制使得能够有效地访问包括M个模块的交错存储器系统，M是（2n + 1）或（2n-1），n是正整数。 在接收到地址N时，控制器执行移位和加/减操作，以基于N​​在M的二项式系列展开来获得N除以M的商。控制器基于商来计算N的余数除以M。 然后，控制器基于剩余部分访问存储器中的一个模块。

公开(公告)号：US20150269083A1

公开(公告)日：2015-09-24

申请号：US14221491

申请日：2014-03-21

申请人： Altug Koker ,  Aditya Navale

发明人： Altug Koker ,  Aditya Navale

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/0871 ,  G06F12/0875 ,  G09G2360/121 ,  Y02D10/13

摘要： Technologies are presented that allow a portion of a cache to be used as a front memory when there is dynamic need based on system demand. A computing system may include at least one processor, a memory controlled by a controller and communicatively coupled with the at least one processor, a cache communicatively coupled with the at least one processor and the memory, and mapping logic communicatively coupled with the at least one processor, the memory, and the cache. The mapping logic may map a portion of the cache to a portion of the memory, wherein the portion of the cache is to be used by the at least one processor as a local memory, and wherein the mapping is dynamic based on system demand and managed by the controller in a physical address domain.

摘要翻译： 当存在基于系统需求的动态需求时，提供允许一部分高速缓存用作前端存储器的技术。 计算系统可以包括至少一个处理器，由控制器控制并与所述至少一个处理器通信耦合的存储器，与所述至少一个处理器和所述存储器通信地耦合的高速缓存器，以及与所述至少一个处理器通信耦合的映射逻辑 处理器，内存和缓存。 所述映射逻辑可将所述高速缓存的一部分映射到所述存储器的一部分，其中所述高速缓存的所述部分将由所述至少一个处理器用作本地存储器，并且其中所述映射基于系统需求而动态地被管理 由控制器在物理地址域中。

公开(公告)号：US09064437B2

公开(公告)日：2015-06-23

申请号：US13707930

申请日：2012-12-07

申请人： Hema Chand Nalluri ,  Aditya Navale

发明人： Hema Chand Nalluri ,  Aditya Navale

IPC分类号： G09G5/36 ,  G09G5/00 ,  G06T1/20 ,  G06F9/52

CPC分类号： G06T1/20 ,  G06F9/48 ,  G06F9/52 ,  G06F15/167 ,  G09G5/001

摘要： Memory-based semaphore are described that are useful for synchronizing operations between different processing engines. In one example, operations include executing a context at a producer engine, the executing including updating a memory register, and sending a signal from the producer engine to a consumer engine that the memory register has been updated, the signal including a Context ID to identify a context to be executed by the consumer engine to update the register.

摘要翻译： 描述了基于内存的信号量，其用于在不同处理引擎之间同步操作。 在一个示例中，操作包括在生成器引擎处执行上下文，执行包括更新存储器寄存器，以及将生成器引擎的信号发送到已更新存储器寄存器的消费者引擎，该信号包括识别的上下文ID 由消费者引擎执行以更新寄存器的上下文。

公开(公告)号：US20140306949A1

公开(公告)日：2014-10-16

申请号：US13976843

申请日：2011-11-18

申请人： Peter L. Doyle ,  Jeffery S. Boles ,  Arthur D. Hunter Jr. ,  Altug Koker ,  Aditya Navale

发明人： Peter L. Doyle ,  Jeffery S. Boles ,  Arthur D. Hunter Jr. ,  Altug Koker ,  Aditya Navale

IPC分类号： G06T1/20 ,  G06T15/10 ,  G06T15/00

CPC分类号： G06T1/20 ,  G06T15/005 ,  G06T15/10 ,  G06T2200/28 ,  G06T2210/52

摘要： Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.

摘要翻译： 描述了系统，装置和方法，包括将批量的几何对象分发到多核系统，在每个处理器核心处，对相应批次的几何对象执行顶点处理和几何设置处理，将顶点处理结果存储到所有可访问的共享存储器 的核心，并将几何设置处理结果存储在本地存储中。 然后，每个特定核心可以使用从特定核心内的本地存储器获得的几何设置结果以及至少一个其他处理器核心的本地存储来执行光栅化。

公开(公告)号：US20140104287A1

公开(公告)日：2014-04-17

申请号：US13649798

申请日：2012-10-11

申请人： Hema C. Nalluri ,  Aditya Navale ,  Murali Ramadoss

发明人： Hema C. Nalluri ,  Aditya Navale ,  Murali Ramadoss

IPC分类号： G06T15/00

CPC分类号： G06F21/74 ,  G06F21/84 ,  G06T15/005

摘要： Techniques are disclosed for processing rendering engine workload of a graphics system in a secure fashion, wherein at least some security processing of the workload is offloaded from software-based security parsing to hardware-based security parsing. In some embodiments, commands from a given application are received by a user mode driver (UMD), which is configured to generate a command buffer delineated into privileged and/or non-privileged command sections. The delineated command buffer can then be passed by the UMD to a kernel-mode driver (KMD), which is configured to parse and validate only privileged buffer sections, but to issue all other batch buffers with a privilege indicator set to non-privileged. A graphics processing unit (GPU) can receive the privilege-designated batch buffers from the KMD, and is configured to disallow execution of any privileged command from a non-privileged batch buffer, while any privileged commands from privileged batch buffers are unrestricted by the GPU

摘要翻译： 公开了用于以安全方式处理图形系统的渲染引擎工作负载的技术，其中将工作负载的至少一些安全处理从基于软件的安全解析卸载到基于硬件的安全解析。 在一些实施例中，来自给定应用的命令由用户模式驱动程序（UMD）接收，用户模式驱动程序（UMD）被配置为生成描绘为特权和/或非特权命令部分的命令缓冲器。 所描绘的命令缓冲区然后可以被UMD传递给内核模式驱动程序（KMD），该驱动程序被配置为仅解析和验证特权缓冲区段，而是发出所有其他批处理缓冲区，其特权指示符设置为非特权。 图形处理单元（GPU）可以从KMD接收特权指定的批量缓冲区，并且配置为不允许从非特权批处理缓冲区执行任何特权命令，而来自特权批处理缓冲区的任何特权命令都不受GPU限制

公开(公告)号：US20130298124A1

公开(公告)日：2013-11-07

申请号：US13932963

申请日：2013-07-01

申请人： Balaji Vembu ,  Aditya Navale ,  Wishwesh Gandhi

发明人： Balaji Vembu ,  Aditya Navale ,  Wishwesh Gandhi

IPC分类号： G06F9/455

CPC分类号： G06F12/1009 ,  G06F9/4401 ,  G06F9/4403 ,  G06F9/4411 ,  G06F9/45533 ,  G06F9/45558 ,  G06F12/109 ,  G06F13/28 ,  G06F2009/45579 ,  G06F2009/45583 ,  G06F2212/152 ,  G06T1/60

摘要： A method and apparatus for creating, updating, and using guest physical address (GPA) to host physical address (HPA) shadow translation tables for translating GPAs of graphics data direct memory access (DMA) requests of a computing environment implementing a virtual machine monitor to support virtual machines. The requests may be sent through a render or display path of the computing environment from one or more virtual machines, transparently with respect to the virtual machine monitor. The creating, updating, and using may be performed by a memory controller detecting entries sent to existing global and page directory tables, forking off shadow table entries from the detected entries, and translating GPAs to HPAs for the shadow table entries.

摘要翻译： 一种用于创建，更新和使用访客物理地址（GPA）以主机物理地址（HPA）影子转换表的方法和装置，用于将实现虚拟机监视器的计算环境的图形数据直接存储器访问（DMA）请求的GPA转换为 支持虚拟机。 可以通过虚拟机监视器透明地从一个或多个虚拟机通过计算环境的呈现或显示路径发送请求。 创建，更新和使用可以由存储器控制器执行，该存储器控制器检测发送到现有全局和页目录表的条目，从检测到的条目中分离影子表条目，以及将影子表条目的GPA转换为HPA。