公开(公告)号：US09075741B2

公开(公告)日：2015-07-07

申请号：US13327845

申请日：2011-12-16

申请人： Altug Koker ,  Shailesh Shah ,  Aditya Navale ,  Murali Ramadoss ,  Satish K. Damaraju

发明人： Altug Koker ,  Shailesh Shah ,  Aditya Navale ,  Murali Ramadoss ,  Satish K. Damaraju

IPC分类号： G06F11/00 ,  G06F11/10 ,  H03M13/09 ,  H04L1/00 ,  H03M13/11

CPC分类号： G06F11/1048 ,  G06F11/10 ,  G06F11/1008 ,  G06F11/1076 ,  H03M13/09 ,  H03M13/11 ,  H04L1/0057

摘要： Embodiments of an invention for dynamic error correction using parity and redundant rows are disclosed. In one embodiment, an apparatus includes a storage structure, parity logic, an error storage space, and an error event generator. The storage structure is to store a plurality of data values. The parity logic is to detect a parity error in a data value stored in the storage structure. The error storage space is to store an indication of a detection of the parity error. The error event generator is to generate an event in response to the indication of the parity error being stored in the error storage space.

摘要翻译： 公开了使用奇偶校验和冗余行的动态纠错的发明的实施例。 在一个实施例中，装置包括存储结构，奇偶校验逻辑，错误存储空间和错误事件发生器。 存储结构是存储多个数据值。 奇偶校验逻辑是检测存储在存储结构中的数据值中的奇偶校验错误。 错误存储空间是存储奇偶校验错误检测的指示。 错误事件发生器响应于存储在错误存储空间中的奇偶校验错误的指示而生成事件。

公开(公告)号：US20140267323A1

公开(公告)日：2014-09-18

申请号：US13851400

申请日：2013-03-27

申请人： Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Aditya Navale

发明人： Altug Koker ,  Balaji Vembu ,  Murali Ramadoss ,  Aditya Navale

IPC分类号： G06T1/60

CPC分类号： G06T1/60 ,  G06F9/485 ,  G06F12/1009 ,  G06F12/128 ,  G06T1/20

摘要： An electronic device is described herein. The electronic device may include a page walker module to receive a page request of a graphics processing unit (GPU). The page walker module may detect a page fault associated with the page request. The electronic device may include a controller, at least partially comprising hardware logic. The controller is to monitor execution of the page request having the page fault. The controller determines whether to suspend execution of a work item at the GPU associated with the page request having the page fault, or to continue execution of the work item based on factors associated with the page request.

摘要翻译： 本文描述了一种电子设备。 电子设备可以包括页面助行器模块，用于接收图形处理单元（GPU）的页面请求。 页面助行器模块可以检测与页面请求相关联的页面错误。 电子设备可以包括至少部分地包括硬件逻辑的控制器。 控制器将监视具有页面错误的页面请求的执行。 控制器确定是否在与具有页面错误的页面请求相关联的GPU处挂起工作项的执行，或者基于与页面请求相关联的因素来继续执行工作项。

公开(公告)号：US20140068626A1

公开(公告)日：2014-03-06

申请号：US13993089

申请日：2011-12-30

申请人： Altug Koker ,  Aditya Navale ,  Balaji Vembu ,  Murali Ramadoss

发明人： Altug Koker ,  Aditya Navale ,  Balaji Vembu ,  Murali Ramadoss

IPC分类号： G06F9/50

CPC分类号： G06F9/50 ,  G06F9/4812 ,  G06F9/545 ,  G06F12/1491 ,  G06F15/167

摘要： Transitions to ring 0, each time an application wants to use an adjunct processor, are avoided, saving central processor operating cycles and improving efficiency. Instead, initially each application is registered and setup to use adjunct processor resources in ring 3.

摘要翻译： 每次应用程序想要使用辅助处理器时，转换到0，避免中断处理器运行周期并提高效率。 相反，最初每个应用程序都被注册并设置为在环3中使用辅助处理器资源。

公开(公告)号：US20190303334A1

公开(公告)日：2019-10-03

申请号：US16447025

申请日：2019-06-20

申请人： Bryan R. White ,  Aravindh Anantaraman ,  Ankur Shah ,  Altug Koker ,  David Puffer ,  Aditya Navale

发明人： Bryan R. White ,  Aravindh Anantaraman ,  Ankur Shah ,  Altug Koker ,  David Puffer ,  Aditya Navale

IPC分类号： G06F13/40 ,  G06F13/42 ,  G06T1/20

摘要： In one embodiment, a method includes: receiving, in a root tile of an accelerator device having a plurality of tiles, a message from a processor, the message comprising a register write request to a register of a first remote tile of the plurality of remote tiles; decoding, in an endpoint controller of the root tile, a system address of the message to identify a destination tile for the message, based at least in part on a base address register decode of the system address; and in response to identifying the first remote tile as the destination tile, updating a first portion of an address offset field of the system address to a predetermined value and directing the message to the first remote tile coupled to the root tile via a sideband interconnect. Other embodiments are described and claimed.

公开(公告)号：US20150103084A1

公开(公告)日：2015-04-16

申请号：US14050626

申请日：2013-10-10

申请人： Hema C. Nalluri ,  Aditya Navale ,  Altug Koker

发明人： Hema C. Nalluri ,  Aditya Navale ,  Altug Koker

IPC分类号： G06T1/20

CPC分类号： G06T1/20

摘要： Methods and systems may provide for storing a set of post-synchronization operations to a graphics memory and sending a flush marker to a graphics pipeline. Additionally, the set of post-synchronization operations may be processed in response to the flush marker exiting the graphics pipeline. In one example, the set of post-synchronization operations includes one or more atomic operations. Moreover, the set of post-synchronization operations may be obtained from an inline portion of an atomics command.

摘要翻译： 方法和系统可以提供将一组后同步操作存储到图形存储器并且向图形流水线发送冲洗标记。 另外，可以响应于离开图形管线的冲洗标记来处理该后同步操作的集合。 在一个示例中，该后同步操作集合包括一个或多个原子操作。 此外，可以从原子命令的内联部分获得该后同步操作的集合。

公开(公告)号：US20130031333A1

公开(公告)日：2013-01-31

申请号：US13191327

申请日：2011-07-26

申请人： Rajesh M. Sankaran ,  Altug Koker ,  Philip R. Lantz ,  Asit K. Mallick ,  James B. Crossland ,  Aditya Navale ,  Gilbert Neiger ,  Andrew V. Anderson

发明人： Rajesh M. Sankaran ,  Altug Koker ,  Philip R. Lantz ,  Asit K. Mallick ,  James B. Crossland ,  Aditya Navale ,  Gilbert Neiger ,  Andrew V. Anderson

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F12/1081 ,  G06F2212/1016 ,  G06F2212/1048 ,  G06F2212/303 ,  G06F2212/682 ,  G06F2212/683

摘要： Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

摘要翻译： 公开了用于在多核系统中共享虚拟存储器的异构设备的有效TLB（转换后备缓冲器）击穿的方法和装置。 用于有效的TLB击倒的装置的实施例可以包括用于存储虚拟地址转换条目的TLB和与TLB耦合的存储器管理单元，以维护对应于虚拟地址转换条目的PASID（进程地址空间标识符）状态条目 。 PASID状态条目可以包括活动参考状态和惰性无效状态。 响应于从多核系统中的设备接收到PASID状态更新请求并且读取PASID状态条目的惰性无效状态，存储器管理单元可执行PASID状态条目的原子修改。 存储器管理单元可以在响应于相应的惰性无效化状态的激活之前向设备发送PASID状态更新响应以同步TLB条目。

公开(公告)号：US09619855B2

公开(公告)日：2017-04-11

申请号：US13976843

申请日：2011-11-18

申请人： Peter L. Doyle ,  Jeffery S. Boles ,  Arthur D. Hunter Jr. ,  Altug Koker ,  Aditya Navale

发明人： Peter L. Doyle ,  Jeffery S. Boles ,  Arthur D. Hunter Jr. ,  Altug Koker ,  Aditya Navale

IPC分类号： G06T15/00 ,  G06T1/20 ,  G06T15/10

CPC分类号： G06T1/20 ,  G06T15/005 ,  G06T15/10 ,  G06T2200/28 ,  G06T2210/52

摘要： Systems, apparatus and methods are described including distributing batches of geometric objects to a multi-core system, at each processor core, performing vertex processing and geometry setup processing on the corresponding batch of geometric objects, storing the vertex processing results shared memory accessible to all of the cores, and storing the geometry setup processing results in local storage. Each particular core may then perform rasterization using geometry setup results obtained from local storage within the particular core and from local storage of at least one of the other processor cores.

公开(公告)号：US20160189681A1

公开(公告)日：2016-06-30

申请号：US14582972

申请日：2014-12-24

申请人： Bryan R. White ,  Balaji Vembu ,  Murali Ramadoss ,  Altug Koker ,  Aditya Navale

发明人： Bryan R. White ,  Balaji Vembu ,  Murali Ramadoss ,  Altug Koker ,  Aditya Navale

IPC分类号： G09G5/18 ,  G06T1/60 ,  G06T1/20

CPC分类号： G09G5/18 ,  G06T1/20 ,  G09G5/026 ,  G09G5/14 ,  G09G5/363 ,  G09G2320/106 ,  G09G2340/02 ,  G09G2360/121 ,  G09G2360/18 ,  G09G2370/16

摘要： Described herein are technologies related to a ensuring that graphics commands and graphics context are offloading and scheduled for consumption as the commands and graphics context are sent from coherent to non-coherent memory/fabric in a “processor to processor” handoff or transaction.

摘要翻译： 这里描述的是与在“处理器到处理器”切换或事务中的命令和图形上下文从相干到非相干存储器/结构发送相关的确保图形命令和图形上下文被卸载并被调度用于消费的技术。

公开(公告)号：US20140375661A1

公开(公告)日：2014-12-25

申请号：US14124845

申请日：2013-06-24

申请人： Altug Koker ,  Aditya Navale

发明人： Altug Koker ,  Aditya Navale

IPC分类号： G06T1/60 ,  G06F12/08

CPC分类号： G06T1/60 ,  G06F12/0802 ,  G06F2212/455 ,  G09G5/363 ,  G09G5/393 ,  G09G2360/121 ,  G09G2360/122

摘要： Systems and methods may provide for identifying a tile associated with an image and ordering an entirety of the tile into a linear stream of pages associated with a frame buffer. Additionally, the linear stream of pages may be allocated to a cache. In one example, the linear stream of pages is allocated to the cache in accordance with a fixed set selection policy of the cache.

摘要翻译： 系统和方法可以提供用于识别与图像相关联的瓦片，并将瓦片的整体排列成与帧缓冲器相关联的页面的线性流。 另外，可以将线性的页面流分配给高速缓存。 在一个示例中，根据高速缓存的固定集合选择策略将页面的线性流分配给高速缓存。

公开(公告)号：US20140025908A1

公开(公告)日：2014-01-23

申请号：US13993680

申请日：2012-06-11

申请人： Saurabh Sharma ,  Altug Koker ,  Aditya Navale

发明人： Saurabh Sharma ,  Altug Koker ,  Aditya Navale

IPC分类号： G06F12/06

CPC分类号： G06F12/0607 ,  G06F2212/302

摘要： A mechanism implemented by a controller enables efficient access to an interleaved memory system that includes M modules, M being (2n+1) or (2n−1), n being a positive integer number. Upon receiving an address N, the controller performs shift and add/subtract operations to obtain a quotient of N divided by M based on a binomial series expansion of N over M. The controller computes a remainder of N divided by M based on the quotient. The controller then accesses one of the modules in the memory based on the remainder.

摘要翻译： 由控制器实现的机制使得能够有效地访问包括M个模块的交错存储器系统，M是（2n + 1）或（2n-1），n是正整数。 在接收到地址N时，控制器执行移位和加/减操作，以基于N​​在M的二项式系列展开来获得N除以M的商。控制器基于商来计算N的余数除以M。 然后，控制器基于剩余部分访问存储器中的一个模块。