公开(公告)号：US07643203B2

公开(公告)日：2010-01-05

申请号：US11401023

申请日：2006-04-10

申请人： Evgeni Gousev ,  Gang Xu ,  Marek Mienko

发明人： Evgeni Gousev ,  Gang Xu ,  Marek Mienko

IPC分类号： G02B26/00 ,  G02B26/08 ,  G02F1/29

CPC分类号： G02B26/001 ,  Y10T29/49124

摘要： Broad band white color can be achieved in MEMS display devices by incorporating a material having an extinction coefficient (k) below a threshold value for wavelength of light within an operative optical range of the interferometric modulator. One embodiment provides a method of making the MEMS display device comprising depositing said material over at least a portion of a transparent substrate, depositing a dielectric layer over the layer of material, forming a sacrificial layer over the dielectric, depositing an electrically conductive layer on the sacrificial layer, and forming a cavity by removing at least a portion of the sacrificial layer. The suitable material may comprise germanium, germanium alloy of various compositions, doped germanium or doped germanium-containing alloys, and may be deposited over the transparent substrate, incorporated within the transparent substrate or the dielectric layer.

摘要翻译： 通过在干涉式调制器的可操作光学范围内并入具有低于阈值的消光系数（k）的材料，可以在MEMS显示装置中实现宽带白色。 一个实施例提供了一种制造MEMS显示装置的方法，包括在透明基板的至少一部分上沉积所述材料，在所述材料层上沉积介电层，在所述电介质层上形成牺牲层，在所述电介质层上沉积导电层 牺牲层，并且通过去除牺牲层的至少一部分来形成空腔。 合适的材料可以包括各种组成的锗，锗合金，掺杂的锗或掺杂的含锗合金，并且可以沉积在透明衬底上，并入透明衬底或电介质层中。

公开(公告)号：US20080026551A1

公开(公告)日：2008-01-31

申请号：US11830277

申请日：2007-07-30

申请人： Cyril Cabral ,  Chester Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam Shahidi ,  Michelle Steen ,  Clement Wann

发明人： Cyril Cabral ,  Chester Dziobkowski ,  Sunfei Fang ,  Evgeni Gousev ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Ghavam Shahidi ,  Michelle Steen ,  Clement Wann

IPC分类号： H01L21/3205

CPC分类号： H01L29/66507 ,  H01L21/28097 ,  H01L21/823443 ,  H01L29/66545

摘要： An advanced gate structure that includes a filly silicided metal gate and silicided source and drain regions in which the fully silicided metal gate has a thickness that is greater than the thickness of the silicided source/drain regions is provided. A method of forming the advanced gate structure is also provided in which the silicided source and drain regions are formed prior to formation of the silicided metal gate region.

摘要翻译： 提供了一种先进的栅极结构，其包括硅化金属栅极和硅化源极和漏极区域，其中完全硅化金属栅极的厚度大于硅化物源极/漏极区域的厚度。 还提供了形成高级栅极结构的方法，其中在形成硅化金属栅极区之前形成硅化源极和漏极区。

公开(公告)号：US20070090471A1

公开(公告)日：2007-04-26

申请号：US11259644

申请日：2005-10-26

申请人： Eduard Cartier ,  Mathew Copel ,  Martin Frank ,  Evgeni Gousev ,  Paul Jamison ,  Rajarao Jammy ,  Barry Linder ,  Vijay Narayanan

发明人： Eduard Cartier ,  Mathew Copel ,  Martin Frank ,  Evgeni Gousev ,  Paul Jamison ,  Rajarao Jammy ,  Barry Linder ,  Vijay Narayanan

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

摘要翻译： 一种半导体结构，特别是pFET，其包括介电常数大于SiO 2的介电常数和大于50％的Ge或Si含量的至少一种其它装置， 提供材料堆栈工程的阈值/平带电压调谐。 本发明中考虑的其它方法包括例如在用于电荷固定的电介质的顶部和/或通过形成工程化的沟道区域之间使用绝缘夹层。 本发明还涉及一种制造这种CMOS结构的方法。

公开(公告)号：US20050258491A1

公开(公告)日：2005-11-24

申请号：US10845719

申请日：2004-05-14

申请人： Nestor Bojarczuk ,  Eduard Cartier ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Vijay Narayanan

发明人： Nestor Bojarczuk ,  Eduard Cartier ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Vijay Narayanan

IPC分类号： H01L21/8234 ,  H01L21/28 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/49 ,  H01L29/51 ,  H01L29/76 ,  H01L29/78 ,  H01L29/786 ,  H01L51/00 ,  H01L51/05

CPC分类号： H01L21/28202 ,  H01L21/28194 ,  H01L21/823857 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： An insulating interlayer for use in complementary metal oxide semiconductor (CMOS) that prevents unwanted shifts in threshold voltage and flatband voltage is provided. The insulating interlayer is located between a gate dielectric having a dielectric constant of greater than 4.0 and a Si-containing gate conductor. The insulating interlayer of the present invention is any metal nitride, that optionally may include oxygen, that is capable of stabilizing the threshold and flatband voltages. In a preferred embodiment, the insulating interlayer is aluminum nitride or aluminum oxynitride and the gate dielectric is hafnium oxide, hafnium silicate or hafnium silicon oxynitride. The present invention is particularly useful in stabilizing the threshold and flatband voltage of p-type field effect transistors.

摘要翻译： 提供了用于防止阈值电压和平带电压的不期望的偏移的互补金属氧化物半导体（CMOS）中的绝缘夹层。 绝缘中间层位于介电常数大于4.0的栅极电介质和含Si的栅极导体之间​​。 本发明的绝缘中间层是能够稳定阈值和平带电压的任何金属氮化物，其可任选地包括氧。 在优选实施例中，绝缘中间层为氮化铝或氮氧化铝，栅极电介质为氧化铪，硅酸铪或铪硅氮氧化物。 本发明在稳定p型场效应晶体管的阈值和平带电压方面特别有用。

公开(公告)号：US20050026459A1

公开(公告)日：2005-02-03

申请号：US10630970

申请日：2003-07-31

申请人： David O'Meara ,  Cory Wajda ,  Anthony Dip ,  Michael Toeller ,  Toshihara Furukawa ,  Kristen Scheer ,  Alessandro Callegari ,  Fred Buehrer ,  Sufi Zafar ,  Evgeni Gousev ,  Anthony Chou ,  Paul Higgins

发明人： David O'Meara ,  Cory Wajda ,  Anthony Dip ,  Michael Toeller ,  Toshihara Furukawa ,  Kristen Scheer ,  Alessandro Callegari ,  Fred Buehrer ,  Sufi Zafar ,  Evgeni Gousev ,  Anthony Chou ,  Paul Higgins

IPC分类号： C23C16/30 ,  H01L21/00 ,  H01L21/28 ,  H01L21/314 ,  H01L21/316 ,  H01L29/51 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28185 ,  C23C16/308 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02249 ,  H01L21/02255 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/31604 ,  H01L21/31616 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31662 ,  H01L21/67098 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： Ultra-thin oxynitride layers are formed utilizing low-pressure processing to achieve self-limiting oxidation of substrates and provide ultra-thin oxynitride. The substrates to be processed can contain an initial dielectric layer such as an oxide layer, an oxynitride layer, or a nitride layer, or alternatively can lack an initial dielectric layer. The processing can be carried out using a batch type process chamber or a single-wafer process chamber.

摘要翻译： 使用低压处理形成超薄氧氮化物层，以实现衬底的自限制氧化并提供超薄氧氮化物。 要处理的基板可以包含初始介电层，例如氧化物层，氧氮化物层或氮化物层，或者可以缺少初始介电层。 处理可以使用间歇式处理室或单晶片处理室进行。

公开(公告)号：US08410690B2

公开(公告)日：2013-04-02

申请号：US12371302

申请日：2009-02-13

申请人： Bangalore R. Natarajan ,  Evgeni Gousev ,  Kristopher A. Lavery

发明人： Bangalore R. Natarajan ,  Evgeni Gousev ,  Kristopher A. Lavery

IPC分类号： B01J20/00

CPC分类号： B01J20/2808 ,  B01D53/261 ,  B01D53/28 ,  B01D2253/108 ,  B01J20/18 ,  B01J20/183 ,  B01J20/2803 ,  B01J2220/42 ,  B81B2201/047 ,  B81C1/00285 ,  B81C2201/112 ,  H01L23/26 ,  H01L51/5259 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/1433 ,  Y10T156/10 ,  H01L2924/00

摘要： Systems and methods for providing MEMS devices with integrated desiccant are provided. In one embodiment, a dry composition comprising desiccant is impact sprayed onto the backplate or substrate of a MEMS device, and becomes fused with the substrate. In another embodiment, the desiccant is impact sprayed such that the desiccant adheres to the impact sprayed surface. In yet another embodiment, the impact-sprayed surface is impregnated with the desiccant. In still another embodiment, the desiccant is combined with a suitable inorganic binder, then impact sprayed such that the desiccant adheres to the impact sprayed surface. In yet a further embodiment, the desiccant is micronized or pulverized into a powder of desired particle size, and then impact sprayed onto a surface. Thus, the desiccant particles or powder are fused onto the target surface through the impact spraying process.

摘要翻译： 提供了提供MEMS器件集成干燥剂的系统和方法。 在一个实施方案中，将包含干燥剂的干组合物冲击喷射到MEMS装置的背板或基板上，并与基底熔合。 在另一个实施方案中，干燥剂被冲击喷雾，使得干燥剂粘附到冲击喷涂表面上。 在另一个实施例中，冲击喷射表面用干燥剂浸渍。 在另一个实施方案中，将干燥剂与合适的无机粘合剂组合，然后冲洗喷雾，使得干燥剂粘附到冲击喷涂表面。 在又一个实施方案中，干燥剂被微粉化或粉碎成所需粒度的粉末，然后冲击喷涂到表面上。 因此，干燥剂颗粒或粉末通过冲击喷涂工艺熔合到目标表面上。

公开(公告)号：US08218228B2

公开(公告)日：2012-07-10

申请号：US12642421

申请日：2009-12-18

申请人： Je-Hsiung Lan ,  Evgeni Gousev ,  Ernest Tadashi Ozaki

发明人： Je-Hsiung Lan ,  Evgeni Gousev ,  Ernest Tadashi Ozaki

IPC分类号： G02B26/00

CPC分类号： H01G5/16 ,  G02B26/001

摘要： A two-terminal, variable capacitance device is described that is constructed by connecting multiple MEMS devices having different actuation or “pull in” voltages in parallel.

摘要翻译： 描述了通过并联具有不同驱动或“拉入”电压的多个MEMS器件构成的两端可变电容器件。

公开(公告)号：US08153514B2

公开(公告)日：2012-04-10

申请号：US12187767

申请日：2008-08-07

申请人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph F. Shepard, Jr. ,  Sufi Zafar

发明人： Wanda Andreoni ,  Alessandro C. Callegari ,  Eduard A. Cartier ,  Alessandro Curioni ,  Christopher P. D'Emic ,  Evgeni Gousev ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Carlo A. Pignedoli ,  Joseph F. Shepard, Jr. ,  Sufi Zafar

IPC分类号： H01L21/3205

CPC分类号： H01L21/28176 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/7833 ,  H01L29/78684

摘要： The present invention provides a gate stack structure that has high mobilities and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×1010 charges/cm2 or less, a peak mobility of about 250 cm2V-s or greater and substantially no mobility degradation at about 6.0×1012 inversion charges/cm2 or greater.

摘要翻译： 本发明提供具有高迁移率和低界面电荷的栅叠层结构，以及包括其的半导体器件即金属氧化物半导体场效应晶体管（MOSFET）。 在半导体器件中，本发明的栅极堆叠结构位于衬底和覆盖栅极导体之间​​。 本发明还提供一种制造本发明的栅叠层结构的方法，其中采用了高温退火工艺（大约800℃）。 本发明中使用的高温退火提供了一种栅极叠层结构，其具有约8×10 10电荷/ cm 2或更小的峰值迁移率，约250cm 2 / s或更大的峰迁移率的通过电荷泵浦测量的界面状态密度，以及 在大约6.0×10 12反转电荷/ cm 2或更大时基本上没有迁移率降解。

公开(公告)号：US20110149374A1

公开(公告)日：2011-06-23

申请号：US12642421

申请日：2009-12-18

申请人： Je-Hsiung Lan ,  Evgeni Gousev ,  Ernest Tadashi Ozaki

发明人： Je-Hsiung Lan ,  Evgeni Gousev ,  Ernest Tadashi Ozaki

IPC分类号： G02B26/02 ,  H01G7/00 ,  H01G5/16 ,  H01G5/40 ,  H01L29/93

CPC分类号： H01G5/16 ,  G02B26/001

摘要： A two-terminal, variable capacitance device is described that is constructed by connecting multiple MEMS devices having different actuation or “pull in” voltages in parallel.

摘要翻译： 描述了通过并联具有不同驱动或“拉入”电压的多个MEMS器件构成的两端可变电容器件。

公开(公告)号：US20080032439A1

公开(公告)日：2008-02-07

申请号：US11497726

申请日：2006-08-02

申请人： Xiaoming Yan ,  Brian Arbuckle ,  Evgeni Gousev ,  Ming-Hau Tung

发明人： Xiaoming Yan ,  Brian Arbuckle ,  Evgeni Gousev ,  Ming-Hau Tung

IPC分类号： H01L21/00

CPC分类号： G02B26/001 ,  B81B2201/047 ,  B81C1/00595 ,  B81C2201/0132

摘要： A method for etching a target material in the presence of a structural material with improved selectivity uses a vapor phase etchant and a co-etchant. Embodiments of the method exhibit improved selectivities of from at least about 2-times to at least about 100-times compared with a similar etching process not using a co-etchant. In some embodiments, the target material comprises a metal etchable by the vapor phase etchant. Embodiments of the method are particularly useful in the manufacture of MEMS devices, for example, interferometric modulators. In some embodiments, the target material comprises a metal etchable by the vapor phase etchant, for example, molybdenum and the structural material comprises a dielectric, for example silicon dioxide.

摘要翻译： 在具有改进的选择性的结构材料存在下蚀刻靶材料的方法使用气相蚀刻剂和共蚀刻剂。 与不使用共蚀刻剂的类似蚀刻工艺相比，该方法的实施例表现出从至少约2倍至至少约100倍的改进的选择性。 在一些实施例中，靶材料包括可由气相蚀刻剂蚀刻的金属。 该方法的实施例在MEMS器件（例如干涉式调制器）的制造中特别有用。 在一些实施例中，靶材料包括可由气相蚀刻剂（例如，钼）蚀刻的金属，并且结构材料包括电介质，例如二氧化硅。