公开(公告)号：US10566324B2

公开(公告)日：2020-02-18

申请号：US15599119

申请日：2017-05-18

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/16 ,  H01L23/64 ,  H01L21/82

Abstract: A semiconductor power conversion device includes a plurality of device cells in different portions of the active area, each including a respective gate electrode. The device includes a gate pad having a plurality of integrated resistors, each having a respective resistance. The device includes a first gate bus extending between the gate pad and the plurality of gate electrodes in a first portion of the active area. The plurality of gate electrodes in the first area is electrically connected to an external gate connection via a first integrated resistor and the first gate bus, and wherein the plurality of gate electrodes in a second portion of the active area is electrically connected to the external gate connection via a second integrated resistor, wherein the first and second integrated resistors have substantially different respective resistance values.

公开(公告)号：US10403623B2

公开(公告)日：2019-09-03

申请号：US15643146

申请日：2017-07-06

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov ,  Fabio Carastro ,  Alvaro Jorge Mari Curbelo

IPC: H01L27/06 ,  H01L23/522 ,  H01L23/528 ,  H01L29/423 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/78 ,  H01L27/07

Abstract: A gate network of a silicon-carbide (SiC) power conversion device includes a plurality of gate electrodes of SiC metal-oxide-semiconductor-based (MOS-based) transistor device cells disposed in an active area of the SiC power conversion device, and a gate pad disposed in a gate pad and bus area of the SiC power conversion device. The gate network also includes a gate bus disposed in the gate pad and bus area of the SiC power conversion device, wherein the gate bus extends between and electrically connects the gate pad to at least a portion of the plurality of gate electrodes in the active area of the SiC power conversion device. At least a portion of the gate pad, the gate bus, the plurality of gate electrodes, or a combination thereof, of the gate network have a positive temperature coefficient of resistance greater than approximately 2000 parts-per-million per degree Celsius (ppm/° C.).

公开(公告)号：US20180337171A1

公开(公告)日：2018-11-22

申请号：US15599119

申请日：2017-05-18

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Alexander Viktorovich Bolotnikov

IPC: H01L27/06 ,  H01L29/06 ,  H01L23/528 ,  H01L23/522 ,  H01L29/16 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/3213 ,  H01L21/04 ,  H01L21/82 ,  H01L23/64

Abstract: A semiconductor power conversion device includes a plurality of device cells in different portions of the active area, each including a respective gate electrode. The device includes a gate pad having a plurality of integrated resistors, each having a respective resistance. The device includes a first gate bus extending between the gate pad and the plurality of gate electrodes in a first portion of the active area. The plurality of gate electrodes in the first area is electrically connected to an external gate connection via a first integrated resistor and the first gate bus, and wherein the plurality of gate electrodes in a second portion of the active area is electrically connected to the external gate connection via a second integrated resistor, wherein the first and second integrated resistors have substantially different respective resistance values.

公开(公告)号：US10056457B2

公开(公告)日：2018-08-21

申请号：US15595717

申请日：2017-05-15

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/06 ,  H01L29/16 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66 ,  H01L29/10 ,  H01L29/745 ,  H01L29/739 ,  H01L29/74

CPC classification number: H01L29/1608 ,  H01L21/046 ,  H01L21/0465 ,  H01L29/0623 ,  H01L29/063 ,  H01L29/0646 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/66068 ,  H01L29/7393 ,  H01L29/7395 ,  H01L29/74 ,  H01L29/7455 ,  H01L29/78 ,  H01L29/7802 ,  H01L29/7816

Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of channel region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed channel region extensions have the same conductivity-type as the channel region and extend outwardly from the channel region and into the JFET region of a first device cell such that a distance between the channel region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

公开(公告)号：US20180190791A1

公开(公告)日：2018-07-05

申请号：US15398489

申请日：2017-01-04

Applicant: General Electric Company

Inventor： Victor Mario Torres ,  Reza Ghandi ,  David Alan Lilienfeld ,  Avinash Srikrishnan Kashyap ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/66 ,  H01L29/36 ,  H01L21/265 ,  H01L21/306 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24 ,  H01L29/861

CPC classification number: H01L29/66537 ,  H01L21/26586 ,  H01L21/30604 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/24 ,  H01L29/36 ,  H01L29/7424 ,  H01L29/7811 ,  H01L29/8618

Abstract: The present disclosure relates to a symmetrical, punch-through transient voltage suppression (TVS) device includes a mesa structure disposed on a semiconductor substrate. The mesa structure includes a first semiconductor layer of a first conductivity-type, a second semiconductor layer of a second conductivity-type disposed on the first semiconductor layer, and a third semiconductor layer of the first conductive-type disposed on the second semiconductor layer. The mesa structure also includes beveled sidewalls forming mesa angles with respect to the semiconductor substrate and edge implants disposed at lateral edges of the second semiconductor layer. The edge implants including dopants of the second conductive-type are configured to cause punch-through to occur in a bulk region and not in the lateral edges of the second semiconductor layer.

公开(公告)号：US10002920B1

公开(公告)日：2018-06-19

申请号：US15379214

申请日：2016-12-14

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Reza Ghandi ,  David Alan Lilienfeld ,  Peter Almern Losee

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/36 ,  H01L29/16 ,  H01L29/20 ,  H01L21/265 ,  H01L21/266

Abstract: The subject matter disclosed herein relates to super-junction (SJ) power devices and, more specifically, to edge termination techniques for SJ power devices. A semiconductor super-junction (SJ) device includes one or more epitaxial (epi) layers having a termination region disposed adjacent to an active region. The termination region includes a plurality of vertical pillars of a first and a second conductivity-type, wherein, moving outward from the active region, a respective width of each successive vertical pillar is the same or smaller. The termination region also includes a plurality of compensated regions having a low doping concentration disposed directly between a first side of each vertical pillar of the first conductivity-type and a first side of each vertical pillar of the second conductivity-type, wherein, moving outward from the active region, a respective width of each successive compensated region is the same or greater.

公开(公告)号：US20170338314A1

公开(公告)日：2017-11-23

申请号：US15595643

申请日：2017-05-15

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Peter Almern Losee

IPC: H01L29/16 ,  H01L29/66 ,  H01L21/04 ,  H01L29/78 ,  H01L29/06 ,  H01L29/74 ,  H01L29/739

Abstract: The subject matter disclosed herein relates to semiconductor power devices, such as silicon carbide (SiC) power devices. In particular, the subject matter disclosed herein relates to shielding regions in the form of body region extensions for that reduce the electric field present between the well regions of neighboring device cells of a semiconductor device under reverse bias. The disclosed body region extensions have the same conductivity-type as the body region and extend outwardly from the body region and into the JFET region of a first device cell such that a distance between the body region extension and a region of a neighboring device cell having the same conductivity type is less than or equal to the parallel JFET width. The disclosed shielding regions enable superior performance relative to a conventional stripe device of comparable dimensions, while still providing similar reliability (e.g., long-term, high-temperature stability at reverse bias).

公开(公告)号：US09806157B2

公开(公告)日：2017-10-31

申请号：US14505975

申请日：2014-10-03

Applicant: General Electric Company

Inventor： Alexander Viktorovich Bolotnikov ,  Avinash Srikrishnan Kashyap

IPC: H01L29/16 ,  H01L29/861 ,  H01L29/66 ,  H01L27/02 ,  H01L27/08

CPC classification number: H01L29/1608 ,  H01L27/0255 ,  H01L27/0814 ,  H01L29/6606 ,  H01L29/861

Abstract: A transient voltage suppression (TVS) device and a method of forming the device are provided. The TVS device includes a first layer of wide band-gap semiconductor material formed of a first conductivity type material, a second layer of wide band-gap semiconductor material formed of a second conductivity type material over at least a portion of the first layer, the second layer including a first concentration of dopant. The TVS device further including a third layer of wide band-gap semiconductor material formed of the second conductivity type material over at least a portion of the second layer, the third layer including a second concentration of dopant, the second concentration of dopant being different than the first concentration of dopant. The TVS device further including a fourth layer of wide band-gap semiconductor material formed of the first conductivity type material over at least a portion of the third layer.

公开(公告)号：US20170243970A1

公开(公告)日：2017-08-24

申请号：US15052664

申请日：2016-02-24

Applicant: General Electric Company

Inventor： Peter Almern Losee ,  Ljubisa Dragoljub Stevanovic ,  Greg Thomas Dunne ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/16 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7816 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/41758 ,  H01L29/66068 ,  H01L29/66681 ,  H01L29/7395 ,  H01L29/745 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/8083

Abstract: Embodiments of a silicon carbide (SiC) device are provided herein. In some embodiments, a silicon carbide (SiC) device may include a gate electrode disposed above a SiC semiconductor layer, wherein the SiC semiconductor layer comprises: a drift region having a first conductivity type; a well region disposed adjacent to the drift region, wherein the well region has a second conductivity type; and a source region having the first conductivity type disposed adjacent to the well region, wherein the source region comprises a source contact region and a pinch region, wherein the pinch region is disposed only partially below the gate electrode, wherein a sheet doping density in the pinch region is less than 2.5×1014 cm−2, and wherein the pinch region is configured to deplete at a current density greater than a nominal current density of the SiC device to increase the resistance of the source region.

公开(公告)号：US09735263B2

公开(公告)日：2017-08-15

申请号：US14787545

申请日：2013-11-18

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Stephen Daley Arthur ,  Kevin Sean Matocha ,  Ramakrishna Rao ,  Peter Almern Losee ,  Alexander Viktorovich Bolotnikov

IPC: H01L29/15 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L29/16 ,  H01L27/088 ,  H01L29/10 ,  H03K17/687

CPC classification number: H01L29/7802 ,  H01L27/088 ,  H01L29/1083 ,  H01L29/1608 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66712 ,  H03K17/687

Abstract: An insulated gate field-effect transistor (IGFET) device includes a semiconductor body (200) and a gate oxide (234). The semiconductor body includes a first well region (216) doped with a first type of dopant and a second well region (220) that is doped with an opposite, second type of dopant and is located within the first well region. The gate oxide includes a relatively thinner outer section (244) and a relatively thicker interior section (246). The outer section is disposed over the first well region and the second well region. The interior section is disposed over a junction gate field effect transistor region (218) of the semiconductor body doped with the second type of dopant. A conductive channel is formed through the second well region when a gate signal is applied to a gate contact (250) disposed on the gate oxide.