公开(公告)号：US20180033870A1

公开(公告)日：2018-02-01

申请号：US15219370

申请日：2016-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Xusheng Wu ,  Xintuo Dai

IPC: H01L29/66 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/0653 ,  H01L29/66545 ,  H01L29/7848

Abstract: A method includes forming at least one fin above a semiconductor substrate. An isolation structure is formed adjacent the fin. A liner layer is formed above the isolation structure adjacent an interface between the fin and the isolation structure. The liner layer includes a material different than the isolation structure. A sacrificial gate structure is formed above a portion of the fin and includes a sacrificial gate insulation layer and a sacrificial gate structure. The sacrificial gate structure is removed. The sacrificial gate insulation layer is removed selectively to the liner layer. A replacement gate structure is formed above a portion of the fin in a cavity defined by removing the sacrificial gate structure.

公开(公告)号：US09812365B1

公开(公告)日：2017-11-07

申请号：US15286117

申请日：2016-10-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John H. Zhang ,  Haigou Huang ,  Xusheng Wu ,  Ruilong Xie ,  Stan Tsai

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/823437 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31056 ,  H01L21/31144 ,  H01L29/66545 ,  H01L29/66636

Abstract: One illustrative method disclosed includes, among other things, forming a plurality of gates above a substrate, each of the gates comprising a gate structure and a first layer of a first insulating material positioned on an upper surface of the gate structure, and forming a second layer of a second insulating material above insulating material positioned above the substrate between the laterally spaced apart gates, wherein the first insulating material and the second insulating material are selectively etchable relative to one another. The method may also include selectively removing a portion of the first layer to thereby expose a portion of the gate structure of at least one of the gates, selectively removing the exposed portion of the gate structure so as to thereby define a gate-cut cavity, and forming an insulating gate-cut structure in the gate-cut cavity.

公开(公告)号：US09754837B1

公开(公告)日：2017-09-05

申请号：US15160409

申请日：2016-05-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Jinping Liu ,  Huang Liu ,  Taifong Chao

IPC: H01L29/15 ,  H01L21/8234 ,  H01L21/3105 ,  H01L21/3115 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092

CPC classification number: H01L27/0886 ,  H01L21/28518 ,  H01L21/31053 ,  H01L21/31155 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  H01L29/7856

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming a mask over an oxide layer and an underlying set of fin structures, the set of fin structures including a plurality of fins each having a substrate base and a silicide layer over the substrate base; implanting the oxide layer through an opening in the mask; removing the mask; polishing the oxide layer overlying the set of fin structures after removing the mask to expose the set of fin structures; and forming a nitride layer over the set of fin structures.

公开(公告)号：US09711447B1

公开(公告)日：2017-07-18

申请号：US15290277

申请日：2016-10-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Qiang Fang ,  Daniel W. Fisher ,  Haigou Huang ,  Jinping Liu ,  Haifeng Sheng ,  Zhiguo Sun

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

CPC classification number: H01L23/528 ,  H01L21/76807 ,  H01L21/76829 ,  H01L21/76877 ,  H01L23/53238

Abstract: Methods of lithographic patterning and structures formed by lithographic patterning. A hardmask layer is formed on a dielectric layer, a feature is formed on the hardmask layer, and a mandrel is formed that extends in a first direction across the first feature. The mandrel and the hardmask layer beneath the mandrel are removed to pattern the hardmask layer with the feature masking a section of the hardmask layer. After the hardmask layer is patterned, the dielectric layer is etched to form a first trench and a second trench that are separated by a section of the dielectric layer masked by the section of the hardmask layer. The first trench and the second trench are filled with a conductor layer to respectively form a first wire and a second wire that is separated from the first wire by the section of the dielectric layer.

公开(公告)号：US09698018B1

公开(公告)日：2017-07-04

申请号：US15132589

申请日：2016-04-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xintuo Dai ,  Haigou Huang ,  Jinping Liu

IPC: H01L21/225 ,  H01L29/66 ,  H01L21/8238 ,  H01L27/088 ,  H01L21/02 ,  H01L27/092

CPC classification number: H01L21/2255 ,  H01L21/02129 ,  H01L21/022 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795

Abstract: A method of introducing self-aligned dopants in semiconductor fins and the resulting device are provided. Embodiments include providing semiconductor fins on first and second portions of a substrate; forming a BSG layer on side surfaces of the semiconductor fins on the first portion of the substrate; forming a first SiN layer on the BSG layer; forming a high quality oxide layer over an upper surface of the substrate, the first SiN layer and side surfaces of the semiconductor fins on the second portion of the substrate; forming a PSG layer over the high quality oxide layer on the second portion of the substrate and side surfaces of the semiconductor fins on the second portion of the substrate; and forming a second SiN layer over the high quality oxide layer and the PSG layer.

公开(公告)号：US09466723B1

公开(公告)日：2016-10-11

申请号：US14751718

申请日：2015-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Haigou Huang ,  Qiang Fang ,  Jin Ping Liu ,  Huang Liu

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/28 ,  H01L29/49 ,  H01L21/283 ,  H01L29/66 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L29/7851 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/31053 ,  H01L21/76819 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/535 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method includes forming a placeholder source/drain contact structure above a semiconductor material. A conformal deposition process is performed to form a liner layer above the placeholder contact structure. A dielectric layer is formed above the liner layer. A first planarization process is performed to remove material of the dielectric layer and expose a first top surface of the liner layer above the placeholder contact structure. A first cap layer is formed above the dielectric layer. A second planarization process is performed to remove material of the first cap layer and the liner layer to expose a second top surface of the placeholder contact structure. The placeholder contact structure is removed to define a source/drain contact recess in the dielectric layer. The sidewalls of the dielectric layer in the source/drain contact recess are covered by the liner layer. A conductive material is formed in the contact recess.

Abstract translation: 一种方法包括在半导体材料之上形成占位符源极/漏极接触结构。 执行保形沉积工艺以在占位符接触结构之上形成衬垫层。 在衬层上方形成介电层。 执行第一平面化处理以去除电介质层的材料并将衬垫层的第一顶表面暴露在占位符接触结构之上。 在电介质层上方形成第一盖层。 执行第二平面化处理以去除第一盖层和衬垫层的材料以暴露占位符接触结构的第二顶表面。 去除占位符接触结构以在电介质层中限定源极/漏极接触凹部。 源极/漏极接触凹部中的电介质层的侧壁被衬里层覆盖。 导电材料形成在接触凹部中。

公开(公告)号：US09385192B2

公开(公告)日：2016-07-05

申请号：US14810167

申请日：2015-07-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L21/762 ,  H01L29/06 ,  H01L21/02 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

公开(公告)号：US09123771B2

公开(公告)日：2015-09-01

申请号：US13765723

申请日：2013-02-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hongliang Shen ,  Kyutae Na ,  Sandeep Gaan ,  Hsin-Neng Tai ,  Weihua Tong ,  Sang Cheol Han ,  Tae Hoon Kim ,  Ja Hyung Han ,  Haigou Huang ,  Changyong Xiao ,  Huang Liu ,  Seung Yeon Kim

IPC: H01L21/762 ,  H01L21/02

CPC classification number: H01L29/0649 ,  H01L21/02123 ,  H01L21/76224 ,  H01L21/76229 ,  H01L27/0886

Abstract: Aspects of the present invention generally relate to approaches for forming a semiconductor device such as a TSV device having a “buffer zone” or gap layer between the TSV and transistor(s). The gap layer is typically filled with a low stress thin film fill material that controls stresses and crack formation on the devices. Further, the gap layer ensures a certain spatial distance between TSVs and transistors to reduce the adverse effects of temperature excursion.

Abstract translation: 本发明的方面通常涉及用于形成半导体器件的方法，例如在TSV和晶体管之间具有“缓冲区”或间隙层的TSV器件。 间隙层通常填充有低应力薄膜填充材料，其控制器件上的应力和裂纹形成。 此外，间隙层确保TSV和晶体管之间的一定空间距离，以减少温度偏移的不利影响。

公开(公告)号：US10923388B2

公开(公告)日：2021-02-16

申请号：US16252114

申请日：2019-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou Huang ,  Yuping Ren ,  Paul Ackmann ,  Guoxiang Ning

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/283 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.

公开(公告)号：US10529831B1

公开(公告)日：2020-01-07

申请号：US16054881

申请日：2018-08-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qun Gao ,  Matthew W. Stoker ,  Haigou Huang

IPC: H01L29/78 ,  H01L29/66

Abstract: At least one method, apparatus and system providing semiconductor devices comprising a semiconductor substrate; a first fin and a second fin on the semiconductor substrate; a first epitaxial formation on the first fin and having an inner surface oriented toward the second fin and an outer surface oriented away from the second fin; a second epitaxial formation on the second fin and having an inner surface oriented toward the first fin and an outer surface oriented away from the first fin; and a conformal dielectric layer on at least portions of the inner and outer surfaces of the first epitaxial formation, on at least portions of the inner and outer surfaces of the first epitaxial formation and the second epitaxial formation, and merged between the inner surface of the first epitaxial formation and inner surface of the second epitaxial formation.