公开(公告)号：US20140264617A1

公开(公告)日：2014-09-18

申请号：US14175288

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Juergen Faul ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L27/0883 ,  H01L21/26586 ,  H01L21/28 ,  H01L21/28255 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/51 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66651

Abstract: The present disclosure provides semiconductor device structures with a first PMOS active region and a second PMOS active region provided within a semiconductor substrate. A silicon germanium channel layer is only formed over the second PMOS active region. Gate electrodes are formed over the first and second PMOS active regions, wherein the gate electrode over the second PMOS active region is formed over the silicon germanium channel.

Abstract translation: 本公开提供半导体器件结构，其具有设置在半导体衬底内的第一PMOS有源区和第二PMOS有源区。 硅锗沟道层仅形成在第二PMOS有源区上。 栅电极形成在第一和第二PMOS有源区上，其中第二PMOS有源区上的栅电极形成在硅锗通道上。

公开(公告)号：US20140256135A1

公开(公告)日：2014-09-11

申请号：US13792540

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Peter Javorka ,  Ralf Richter ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L21/308

CPC classification number: H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes the steps of forming a masking layer that covers a P-type transistor and exposes at least a gate cap layer of an N-type transistor, performing a first etching process through the masking layer to remove a portion of the gate cap of the N-type transistor so as to thereby define a reduced thickness gate cap layer for the N-type transistor, removing the masking layer, and performing a common second etching process on the P-type transistor and the N-type transistor that removes a gate cap layer of the P-type transistor and the reduced thickness gate cap of the N-type transistor.

Abstract translation: 本文公开的一种说明性方法包括以下步骤：形成覆盖P型晶体管并暴露N型晶体管的至少栅极帽层的掩模层，通过掩模层执行第一蚀刻工艺以去除部分 N型晶体管的栅极帽，从而限定了用于N型晶体管的减小厚度的栅极盖层，去除掩模层，并对P型晶体管和N型晶体管执行公共的第二蚀刻工艺 其去除了N型晶体管的P型晶体管的栅极盖层和减小厚度的栅极盖。

公开(公告)号：US20140252429A1

公开(公告)日：2014-09-11

申请号：US13792730

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ralf Richter ,  Peter Javorka ,  Jan Hoentschel ,  Stefan Flachowsky

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC classification number: H01L29/42376 ,  H01L21/28008 ,  H01L21/28052 ,  H01L21/28114 ,  H01L21/28123 ,  H01L29/4933 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/78

Abstract: Methods for forming a semiconductor device are provided. In one embodiment, a gate structure having a gate insulating layer and a gate electrode structure formed on the gate insulating layer is provided. The methods provide reducing a dimension of the gate electrode structure relative to the gate insulating layer along a direction extending in parallel to a direction connecting the source and drain. A semiconductor device structure having a gate structure including a gate insulating layer and a gate electrode structure formed above the gate insulating layer is provided, wherein a dimension of the gate electrode structure extending along a direction which is substantially parallel to a direction being oriented from source to drain is reduced relative to a dimension of the gate insulating layer. According to some examples, gate structures are provided having a gate silicon length which is decoupled from the channel width induced by the gate structure.

Abstract translation: 提供了形成半导体器件的方法。 在一个实施例中，提供了一种在栅极绝缘层上形成栅极绝缘层和栅电极结构的栅极结构。 所述方法提供了沿着平行于连接源极和漏极的方向延伸的方向，相对于栅极绝缘层减小栅电极结构的尺寸。 提供一种具有栅极结构的半导体器件结构，该栅极结构包括形成在栅极绝缘层上方的栅极绝缘层和栅电极结构，其中栅电极结构的尺寸沿着基本上平行于源极方向的方向延伸 漏极相对于栅极绝缘层的尺寸减小。 根据一些示例，提供具有栅极硅长度的栅极结构，其与由栅极结构引起的沟道宽度解耦。

公开(公告)号：US08815741B1

公开(公告)日：2014-08-26

申请号：US13793082

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Jan Hoentschel ,  Sven Beyer ,  Peter Javorka

IPC: H01L21/311 ,  H01L21/265

CPC classification number: H01L21/265 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31155 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: A method includes providing a semiconductor structure including a substrate and a transistor element. A layer of a spacer material is deposited over the substrate and the gate structure, wherein the deposited layer of spacer material has an intrinsic stress. Ions are implanted into the layer of spacer material. After the deposition of the layer of spacer material and the implantation of ions into the layer of spacer material, a sidewall spacer is formed at sidewalls of the gate structure from the layer of spacer material.

Abstract translation: 一种方法包括提供包括衬底和晶体管元件的半导体结构。 在衬底和栅极结构上沉积间隔材料层，其中间隔物材料的沉积层具有固有应力。 离子被植入到间隔物材料层中。 在间隔物材料层沉积并将离子注入到间隔物材料层中之后，在间隔物材料层的栅极结构的侧壁处形成侧壁间隔物。

公开(公告)号：US20140131805A1

公开(公告)日：2014-05-15

申请号：US14074905

申请日：2013-11-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephan Kronholz ,  Peter Javorka ,  Roman Boschke

IPC: H01L27/088

CPC classification number: H01L27/088 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

Abstract: A semiconductor device includes a first transistor positioned in and above a first semiconductor region, the first semiconductor region having a first upper surface and including a first semiconductor material. The semiconductor device further includes first raised drain and source portions positioned on the first upper surface of the first semiconductor region, the first drain and source portions including a second semiconductor material having a different material composition from the first semiconductor material. Additionally, the semiconductor device includes a second transistor positioned in and above a second semiconductor region, the second semiconductor region including the first semiconductor material. Finally, the semiconductor device also includes strain-inducing regions embedded in the second semiconductor region, the embedded strain-inducing regions including the second semiconductor material.

Abstract translation: 半导体器件包括位于第一半导体区域中和上方的第一晶体管，所述第一半导体区域具有第一上表面并且包括第一半导体材料。 所述半导体器件还包括位于所述第一半导体区域的所述第一上表面上的第一突起漏极和源极部分，所述第一漏极和源极部分包括具有与所述第一半导体材料不同的材料组成的第二半导体材料。 此外，半导体器件包括位于第二半导体区域中和上方的第二晶体管，第二半导体区域包括第一半导体材料。 最后，半导体器件还包括嵌入在第二半导体区域中的应变诱导区域，包括第二半导体材料的嵌入的应变诱导区域。

公开(公告)号：US20180053829A1

公开(公告)日：2018-02-22

申请号：US15242689

申请日：2016-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Sylvain Henri Baudot ,  Peter Javorka ,  Gerd Zschaetzsch

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L21/28114 ,  H01L29/66628 ,  H01L29/786

Abstract: A method of forming a semiconductor device is provided, wherein the method includes forming a shaped gate structure over an active region, the shaped gate structure comprising a gate dielectric layer and a gate electrode disposed on the gate dielectric layer, and forming raised source/drain regions adjacent to the gate structure, the raised source/drain regions being formed at opposing sides of the shaped gate structure relative to a length direction of the shaped gate structure, wherein the gate electrode has a tapering shape according to which a dimension of the gate electrode along the length direction varies from a maximum value at a lower portion of the gate electrode close to the gate dielectric layer towards a minimal value at a top portion of the gate electrode.

公开(公告)号：US20160300928A1

公开(公告)日：2016-10-13

申请号：US14684559

申请日：2015-04-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jan Hoentschel ,  Stefan Flachowsky ,  Peter Javorka ,  Ralf Richter

IPC: H01L29/66 ,  H01L27/088 ,  H01L21/266 ,  H01L21/8234 ,  H01L21/265

CPC classification number: H01L29/66545 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/665 ,  H01L29/6653

Abstract: A method of manufacturing a semiconductor device is provided including forming replacement gates over a semiconductor layer, forming sidewall spacers at sidewalls of the replacement gates, forming a dielectric layer in interspaces between the sidewall spacers of neighboring replacement gates, removing the replacement gates and sidewall spacers to form openings in the dielectric layer, and forming gate electrodes in the openings.

Abstract translation: 提供了一种制造半导体器件的方法，包括在半导体层上形成替代栅极，在替换栅极的侧壁处形成侧壁间隔物，在相邻替代栅极的侧壁间隔件之间的间隙中形成介电层，去除替换栅极和侧壁间隔物 以在电介质层中形成开口，并在开口中形成栅电极。

公开(公告)号：US09406565B2

公开(公告)日：2016-08-02

申请号：US13842077

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Peter Javorka ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L21/8234 ,  H01L21/266 ,  H01L21/8238 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L21/823418 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656

Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. A first sacrificial oxide layer is formed overlying the semiconductor substrate and a first implant mask is patterned overlying the first sacrificial oxide layer to expose a portion of the first sacrificial oxide layer adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate, through the first sacrificial oxide layer. The first implant mask and the first sacrificial oxide layer are removed after implanting the conductivity determining ions into the semiconductor substrate.

Abstract translation: 本文提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括形成覆盖半导体衬底的栅电极结构。 第一牺牲氧化物层被形成在半导体衬底上，并且第一注入掩模被图案化成覆盖在第一牺牲氧化物层上以暴露与栅电极结构相邻的第一牺牲氧化物层的一部分。 电导率确定离子通过第一牺牲氧化物层注入到半导体衬底中。 在将导电性确定离子注入半导体衬底之后，去除第一注入掩模和第一牺牲氧化物层。

公开(公告)号：US09401423B2

公开(公告)日：2016-07-26

申请号：US13943521

申请日：2013-07-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Stefan Flachowsky

IPC: H01L21/02 ,  H01L29/78 ,  H01L21/28 ,  H01L21/30 ,  H01L21/3115 ,  H01L21/8238

CPC classification number: H01L29/7843 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/3115 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823864

Abstract: When forming transistors with deuterium enhanced gate dielectrics and strained channel regions, the manufacturing processes of strain-inducing dielectric material layers formed above the transistors may be employed to efficiently introduce and diffuse the deuterium to the gate dielectrics. The incorporation of deuterium into the strain-inducing dielectric material layers may be accomplished on the basis of a deposition process in which deuterium is present in the process environment during deposition. The process temperature of the deposition process may be chosen to perform—potentially in combination with further subsequently performed process steps—a sufficient diffusion of deuterium to the gate dielectrics.

Abstract translation: 当用氘增强的栅极电介质和应变通道区形成晶体管时，可以使用在晶体管上方形成的应变诱导电介质材料层的制造工艺来有效地将氘引入和扩散到栅极电介质。 应变诱导电介质材料层中的氘结合可以在沉积过程中基于沉积过程中完成沉积过程，其中氘存在于工艺环境中。 可以选择沉积工艺的工艺温度来执行 - 潜在地与进一步随后执行的工艺步骤组合 - 氘到栅极电介质的充分扩散。

公开(公告)号：US20160005734A1

公开(公告)日：2016-01-07

申请号：US14856065

申请日：2015-09-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Javorka ,  Juergen Faul ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L27/088 ,  H01L29/10

CPC classification number: H01L27/0883 ,  H01L21/26586 ,  H01L21/28 ,  H01L21/28255 ,  H01L21/823412 ,  H01L21/823807 ,  H01L29/1041 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/495 ,  H01L29/51 ,  H01L29/66537 ,  H01L29/6659 ,  H01L29/66651

Abstract: Disclosed is an integrated circuit product comprised of a semiconductor substrate with a first PMOS active region and a second PMOS active region, of which only the second PMOS active region has a silicon germanium layer formed thereon, a first PMOS device formed in and above the first PMOS active region, the first PMOS device having a first gate structure, and a second PMOS device formed in and above the second PMOS active region, the second PMOS device having a second gate structure disposed on the silicon germanium layer.

Abstract translation: 公开了一种集成电路产品，其包括具有第一PMOS有源区和第二PMOS有源区的半导体衬底，其中仅第二PMOS有源区具有形成于其上的锗锗层，形成在第一PMOS有源区和第二PMOS有源区之上的第一PMOS器件 PMOS有源区，第一PMOS器件具有第一栅极结构，以及形成在第二PMOS有源区中和上方的第二PMOS器件，第二PMOS器件具有设置在硅锗层上的第二栅极结构。