公开(公告)号：US20190035888A1

公开(公告)日：2019-01-31

申请号：US15658943

申请日：2017-07-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L29/10 ,  H01L29/786 ,  H01L29/78

Abstract: Structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor. A seed layer is epitaxially grown on a substrate, and a layer stack is epitaxially grown on the seed layer. The layer stack includes a first plurality of semiconductor layers and a second plurality of semiconductor layers alternatingly arranged with the first plurality of semiconductor layers. The layer stack is patterned to form a body feature located on the seed layer. The body feature includes a plurality of nanosheet channel layers patterned from the first plurality of semiconductor layers and a plurality of sacrificial layers patterned from the second plurality of semiconductor layers. Semiconductor material for a source/drain region is epitaxially grown laterally from the nanosheet channel layers and vertically from the seed layer.

公开(公告)号：US10026818B1

公开(公告)日：2018-07-17

申请号：US15410159

申请日：2017-01-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sipeng Gu ,  Xusheng Wu ,  Wenhe Lin ,  Jeffrey Chee

IPC: H01L29/66 ,  H01L29/417 ,  H01L21/321 ,  H01L29/78 ,  H01L29/08 ,  H01L21/265

Abstract: Disclosed are a field effect transistor (FET) and a FET formation method. In the FET, an interlayer dielectric (ILD) layer is positioned laterally adjacent to a sidewall spacer of a replacement metal gate and a cap layer covers the ILD layer, the sidewall spacer and the gate. However, during processing after the gate is formed but before the cap layer is formed, the ILD layer is polished and then recessed such that the top surface of the ILD layer is lower than the top surfaces of the sidewall spacer and the gate. The cap layer is then deposited such that the cap layer is, not only above the top surfaces of the ILD layer, sidewall spacer and gate, but also positioned laterally adjacent to a vertical surface of the sidewall spacer. Recessing the ILD layer prevents shorts between the gate and subsequently formed contacts to the FET source/drain regions.

公开(公告)号：US20180114730A1

公开(公告)日：2018-04-26

申请号：US15334964

申请日：2016-10-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jianwei Peng ,  Xusheng Wu

IPC: H01L21/8238 ,  H01L21/762 ,  H01L21/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a spacer integration scheme for both NFET and PFET devices and methods of manufacture. The structure includes: a plurality of epitaxial grown fin structures for NFET devices having sidewall spacers of a first dimension; and a plurality epitaxial grown fin structures for PFET devices having sidewall spacers of the first dimension.

公开(公告)号：US09865681B1

公开(公告)日：2018-01-09

申请号：US15453170

申请日：2017-03-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng Wu ,  John Zhang ,  Jiehui Shu

IPC: H01L29/06 ,  H01L21/02 ,  H01L21/306 ,  H01L21/28 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02181 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/28088 ,  H01L21/30604 ,  H01L29/42392 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66568

Abstract: Multi-threshold voltage (Vt) nanowire devices are fabricated using a self-aligned methodology where gate cavities having a predetermined geometry are formed proximate to channel regions of respective devices. The gate cavities are then backfilled with a gate conductor. By locally defining the cavity geometry, the thickness of the gate conductor is constrained and hence the threshold voltage for each device can be defined using a single deposition process for the gate conductor layer. The self-aligned nature of the method obviates the need to control gate conductor layer thicknesses using deposition and/or etch processes.

公开(公告)号：US09837553B1

公开(公告)日：2017-12-05

申请号：US15282415

申请日：2016-09-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xusheng Wu ,  John H. Zhang ,  Haigou Huang

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78696 ,  H01L29/0847 ,  H01L29/42372 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/78618 ,  H01L29/78642

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to vertical field effect transistors (VFETs) and methods of manufacture. The VFET includes: one or more vertical fin structures; a source region positioned at a first location on a top surface of the one or more vertical fin structures; a drain region positioned at a second location on the top surface of the one or more vertical fin structures at a predetermined distance away from the source region, along a length thereof; and a gate channel along the predetermined distance and in electrical contact with the source region and the drain region.

公开(公告)号：US20170345913A1

公开(公告)日：2017-11-30

申请号：US15165294

申请日：2016-05-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xintuo Dai ,  Haigou Huang ,  Xusheng Wu

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method includes forming a placeholder gate structure embedded in a dielectric layer. The placeholder gate structure includes a sacrificial material. A first hard mask layer is formed above the dielectric layer. The first hard mask layer and the sacrificial material are the same material. A second hard mask layer is formed above the first hard mask layer. The second hard mask layer is patterned to define an opening therein exposing a portion of the first hard mask layer and being disposed above a portion of the placeholder gate structure. The exposed portion of the first hard mask layer and the portion of the sacrificial material of the placeholder gate structure disposed below the opening are removed to define a gate cut cavity and divide the placeholder gate structure into first and second segments. A dielectric material is formed in the gate cut cavity.

公开(公告)号：US20170338329A1

公开(公告)日：2017-11-23

申请号：US15157868

申请日：2016-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chengwen Pei ,  Xusheng Wu ,  Ziyan Xu

IPC: H01L29/66 ,  H01L21/22 ,  H01L29/207 ,  H01L21/285 ,  H01L21/225 ,  H01L29/78 ,  H01L21/311

CPC classification number: H01L29/66795 ,  H01L21/2225 ,  H01L21/2254 ,  H01L21/28518 ,  H01L21/31144 ,  H01L29/207 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/785

Abstract: Aspects of the present disclosure include fabricating integrated circuit (IC) structures using a boron etch-stop layer, and IC structures with a boron-rich region therein. Methods of forming an IC structure according to the present disclosure can include: growing a conductive epitaxial layer on an upper surface of a semiconductor element; forming a boron etch-stop layer directly on an upper surface of the conductive epitaxial layer; forming an insulator on the boron etch-stop layer; forming an opening within the insulator to expose an upper surface of the boron etch-stop layer; annealing the boron etch-stop layer to drive boron into the conductive epitaxial layer, such that the boron etch-stop layer becomes a boron-rich region; and forming a contact to the boron-rich region within the opening, such that the contact is electrically connected to the semiconductor element through at least the conductive epitaxial layer.

公开(公告)号：US09793358B2

公开(公告)日：2017-10-17

申请号：US14267541

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Xiang Hu ,  Changyong Xiao ,  Wanxun He

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/161 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L29/161 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/7853

Abstract: A non-planar semiconductor structure includes raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon naturally growing into a diamond shape. The surface area of the epitaxial structure may be increased by removing portion(s) thereof. The removal may create a multi-head (e.g., dual-head) epitaxial structure, together with the neck of the raised structure resembling a Y-shape. Raised structures that are not intended to include an epitaxial structure will be masked during epitaxial structure creation and modification. In addition, in order to have a uniform height, the filler material surrounding the raised structures is recessed around those to receive epitaxial structures.

公开(公告)号：US09761594B2

公开(公告)日：2017-09-12

申请号：US14043871

申请日：2013-10-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Bingwu Liu ,  Randy Mann

IPC: H01L27/11 ,  H01L21/265 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/02 ,  H01L21/266 ,  H01L29/78

CPC classification number: H01L27/1104 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0886 ,  H01L29/66803 ,  H01L29/785

Abstract: Approaches for providing a hardmask used during a halo/extension implant of a static random access memory (SRAM) layout for a semiconductor device are disclosed. Specifically, approaches are provided for forming a pull-down (PD) transistor over a substrate; forming a pass-gate (PG) transistor over the substrate; and patterning a hardmask over the device, the hardmask including a first section adjacent the PD transistor and a second section adjacent the PG transistor, wherein a distance between the first section and the PD transistor is shorter than a distance between the second section and the PG transistor. The respective distances between the first section and the PD transistor, and the second section and the PG transistor, are selected to prevent a halo/extension implant from impacting one side of the PD transistor, while allowing the halo/extension implant to impact both sides of the PG transistor.

公开(公告)号：US20170243782A1

公开(公告)日：2017-08-24

申请号：US15047137

申请日：2016-02-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng Wu ,  Hui Zang

IPC: H01L21/762 ,  H01L21/308 ,  H01L27/12 ,  H01L21/311 ,  H01L29/08 ,  H01L29/06 ,  H01L21/84 ,  H01L21/3213

CPC classification number: H01L21/76283 ,  H01L21/308 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0847

Abstract: One illustrative method disclosed includes forming an isolation structure so as to define first and second active regions on the SOI substrate, forming a field effect transistor above the first active region and forming an opening in the second active region that exposes an upper surface of the bulk semiconductor layer in the second active region. In this example, the method further includes performing a common epitaxial growth process so as to form an epi semiconductor material region above each of the source/drain regions of the transistor and to form a unitary epi semiconductor structure above the second active region, wherein the unitary epi semiconductor structure is formed on and in contact with the exposed upper surface of the bulk semiconductor layer within the opening and on and in contact with an upper surface of the active layer in the second active region.