公开(公告)号：US09076846B2

公开(公告)日：2015-07-07

申请号：US14071070

申请日：2013-11-04

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Errol Todd Ryan ,  Kunaljeet Tanwar ,  Xunyuan Zhang

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76814 ,  H01L21/02063 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/32134 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76865 ,  H01L21/76883

Abstract: Methods for fabricating integrated circuits are provided in various exemplary embodiments. In one embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having a first exposed surface including an elemental metal material and a second exposed surface including a barrier material. The elemental metal material has a first etch rate when exposed to a wet etchant and the barrier material has a second etch rate when exposed to the wet etchant. Further, the method includes modifying the first exposed surface to form a modified first exposed surface so as to reduce the first etch rate when exposed to the wet etchant and applying the wet etchant simultaneously to the modified first exposed surface and to the second exposed surface.

Abstract translation: 在各种示例性实施例中提供了用于制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括提供具有包括元素金属材料的第一暴露表面和包括阻挡材料的第二暴露表面的半导体衬底。 当暴露于湿蚀刻剂时，元素金属材料具有第一蚀刻速率，并且当暴露于湿蚀刻剂时，阻挡材料具有第二蚀刻速率。 此外，该方法包括修改第一暴露表面以形成修改的第一暴露表面，以便当暴露于湿蚀刻剂时降低第一蚀刻速率，并将湿蚀刻剂同时施加到经修改的第一暴露表面和第二暴露表面。

公开(公告)号：US20140220775A1

公开(公告)日：2014-08-07

申请号：US13757504

申请日：2013-02-01

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Errol Todd Ryan ,  Kunaljeet Tanwar

IPC: H01L21/768

CPC classification number: H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76883

Abstract: A method for fabricating integrated circuits includes providing a substrate including a protecting layer over an oxide layer and etching a recess through the protecting layer and into the oxide layer. A barrier material is deposited over the substrate to form a barrier layer including a first region in the recess and a second region outside the recess. A conductive material is deposited over the barrier layer and forms an embedded electrical interconnect in the recess and an overburden region outside the recess. The overburden region of the conductive material is removed and a portion of the embedded electrical interconnect is recessed. Thereafter, the barrier layer is etched to remove the second region of the barrier layer and to recess a portion of the first region of the barrier layer. After etching the barrier layer, the protecting layer is removed from the oxide layer.

Abstract translation: 一种用于制造集成电路的方法包括在氧化物层上提供包括保护层的衬底，并蚀刻通过保护层的凹陷并进入氧化物层。 阻挡材料沉积在衬底上以形成包含凹部中的第一区域和凹部外部的第二区域的阻挡层。 导电材料沉积在阻挡层上并在凹槽中形成嵌入的电互连，并且在凹部外部形成覆盖层。 去除导电材料的覆盖层区域，并且嵌入式电互连件的一部分凹陷。 此后，蚀刻阻挡层以去除阻挡层的第二区域并使阻挡层的第一区域的一部分凹陷。 在蚀刻阻挡层之后，从氧化物层去除保护层。

公开(公告)号：US08753975B1

公开(公告)日：2014-06-17

申请号：US13757288

申请日：2013-02-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Larry Zhao ,  Ming He ,  Sean Lin ,  John Iacoponi ,  Errol Todd Ryan

IPC: H01L21/4763

CPC classification number: H01L21/76873 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76856 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method includes forming a trench/via in a layer of insulating material, forming a first layer comprised of silicon or germanium on the insulating material in the trench/via, forming a copper-based seed layer on the first layer, converting at least a portion of the copper-based seed layer into a copper-based nitride layer, depositing a bulk copper-based material on the copper-based nitride layer so as to overfill the trench/via and performing at least one chemical mechanical polishing process to remove excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure. A device includes a layer of insulating material, a copper-based conductive structure positioned in a trench/via within the layer of insulating material and a copper-based nitride layer positioned between the copper-based conductive structure and the layer of insulating material, wherein the copper-based nitride layer contacts both of the copper-based conductive structure and the layer of insulating material.

Abstract translation: 一种方法包括在绝缘材料层中形成沟槽/通孔，在沟槽/通孔中的绝缘材料上形成由硅或锗构成的第一层，在第一层上形成铜基种子层，至少转化为 铜基种子层的一部分成为铜基氮化物层，在铜基氮化物层上沉积大量铜基材料，以覆盖沟槽/通孔，并执行至少一种化学机械抛光工艺以除去过量的 位于沟槽/通孔外部的材料，从而限定铜基导电结构。 一种器件包括绝缘材料层，位于绝缘材料层内的沟槽/通孔中的铜基导电结构以及位于铜基导电结构和绝缘材料层之间的铜基氮化物层，其中 铜基氮化物层接触铜基导电结构和绝缘材料层。

公开(公告)号：US20200066585A1

公开(公告)日：2020-02-27

申请号：US16106246

申请日：2018-08-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sean Xuan Lin ,  Christian Witt ,  Mark V. Raymond ,  Nicholas V. LiCausi ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/532

Abstract: Structures for interconnects and methods of forming interconnects. An interconnect opening in a dielectric layer includes a first portion and a second portion arranged over the first portion. A first conductor layer composed of a first metal is arranged inside the first portion of the interconnect opening. A second conductor layer composed of a second metal is arranged inside the second portion of the interconnect opening. The first metal is ruthenium.

公开(公告)号：US10262892B2

公开(公告)日：2019-04-16

申请号：US15345882

申请日：2016-11-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Frank W. Mont ,  Errol Todd Ryan

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to skip via structures and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer with one or more wiring structures, located above the first wiring layer; a skip via with metallization, which passes through upper wiring levels including the second wiring layer and which makes contact with the one or more wiring structures of the first wiring layer; and a via structure which comprises a protective material and contacts at least one of the one or more wiring structures at the upper wiring level.

公开(公告)号：US10109526B1

公开(公告)日：2018-10-23

申请号：US15609408

申请日：2017-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Nicholas V. LiCausi ,  J. Jay McMahon ,  Ryan S. Smith ,  Errol Todd Ryan ,  Shao Beng Law

IPC: H01L21/768

Abstract: Structures for a skip via and methods of forming a skip via in an interconnect structure. A metallization level is formed that includes a dielectric layer with a top surface. An opening is formed that extends vertically from the top surface of the dielectric layer into the dielectric layer. A dielectric cap layer is deposited on a bottom surface of the opening. A fill layer is formed inside the opening and extends from the top surface of the dielectric layer to the dielectric cap layer on the bottom surface of the opening. A via opening is etched that extends vertically through the fill layer to the dielectric cap layer on the bottom surface of the opening.

公开(公告)号：US20180261457A1

公开(公告)日：2018-09-13

申请号：US15457200

申请日：2017-03-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shao Beng Law ,  Xunyuan Zhang ,  Errol Todd Ryan ,  Nicholas LiCausi

IPC: H01L21/033 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/28556 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/32051 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5283

Abstract: Methods of forming non-mandrel cuts. A dielectric layer is formed on a metal hardmask layer, and a patterned sacrificial layer is formed on the dielectric layer. The dielectric layer is etched to form a non-mandrel cut in the dielectric layer that is vertically aligned with the opening in the patterned sacrificial layer. A metal layer is formed on an area of the metal hardmask layer exposed by the non-mandrel cut in the dielectric layer. The metal hardmask layer is patterned with the metal layer masking the metal hardmask layer over the area.

公开(公告)号：US09570394B1

公开(公告)日：2017-02-14

申请号：US15140808

申请日：2016-04-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan Zhang ,  Nicholas V. LiCausi ,  Errol Todd Ryan

IPC: H01L21/4763 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02 ,  H01L21/285 ,  H01L21/288 ,  H01L21/3205 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/32051 ,  H01L21/02123 ,  H01L21/02164 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/288 ,  H01L21/7684 ,  H01L21/76852 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53242 ,  H01L23/53257

Abstract: Embodiments of the present disclosure may provide methods of forming an IC structure with a pair of metal fins. An IC structure with a pair of metal fins can include two unitary metal fins positioned on a substrate and each including an elongated wire positioned on the substrate and a via positioned directly on a portion of the elongated wire, the elongated wire and the via of each unitary metal fin defining an inverted T-shape, wherein each unitary metal fin includes the elongated wire with a pair of opposing sidewalls substantially coplanar with a pair of opposing sidewalls of the via, and wherein the each unitary metal fin includes a single crystallographic orientation. An insulating layer can be positioned directly laterally between the two unitary metal fins.

Abstract translation: 本公开的实施例可以提供用一对金属翅片形成IC结构的方法。 具有一对金属翅片的IC结构可以包括位于基底上的两个单一金属翅片，每个包括位于基底上的细长线和直接位于细长线的一部分上的通孔，细长线和每个 一体式金属翅片限定了倒T形，其中每个单一金属翅片包括具有一对相对的侧壁的细长线，所述相对的侧壁与通孔的一对相对的侧壁基本共面，并且其中每个单一金属翅片包括单晶取向。 绝缘层可以直接横向放置在两个单一金属翅片之间。

公开(公告)号：US09343408B2

公开(公告)日：2016-05-17

申请号：US14075228

申请日：2013-11-08

Applicant: Intermolecular Inc. ,  GLOBALFOUNDRIES, Inc.

Inventor： Anh Duong ,  Errol Todd Ryan

IPC: H01L23/532 ,  H01L21/3213 ,  C23F1/02 ,  C23F1/18 ,  C23F1/26

CPC classification number: H01L23/5329 ,  C23F1/02 ,  C23F1/18 ,  C23F1/26 ,  H01L21/32134 ,  H01L21/76834 ,  H01L21/76883 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Copper can be etched with selectivity to Ta/TaN barrier liner and SiC hardmask layers, for example, to reduce the potential copper contamination. The copper film can be recessed more than the liner to further enhance the protection. Wet etch solutions including a mixture of HF and H2SO4 can be used for selective etching copper with respect to the liner material, for example, the copper film can be recessed between 2 and 3 nm, and the barrier liner film can be recessed between 1.5 and 2 nm.

Abstract translation: 可以选择性地对Ta / TaN阻挡衬垫和SiC硬掩模层进行蚀刻，例如，以减少潜在的铜污染。 铜膜可以比内衬更凹入，以进一步增强保护。 包括HF和H 2 SO 4的混合物的湿蚀刻溶液可用于相对于衬垫材料选择性蚀刻铜，例如，铜膜可以凹陷在2和3nm之间，并且阻挡衬里膜可以凹入1.5和 2 nm。

公开(公告)号：US20160118292A1

公开(公告)日：2016-04-28

申请号：US14525796

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ming He ,  Errol Todd Ryan ,  Roderick Alan Augur ,  Craig Child ,  Larry Zhao

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect trench in a dielectric layer, and forming a conformal barrier layer overlying the dielectric layer and within the interconnect trench. A barrier spacer is formed by removing the conformal barrier layer from an interconnect trench bottom, and an interconnect is formed within the interconnect trench after forming the barrier spacer. An air gap trench is formed in the dielectric layer adjacent to the barrier spacer, and a top cap is formed overlying the interconnect and the air gap trench, where the top cap bridges the air gap trench to produce an air gap in the air gap trench.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括在电介质层中形成互连沟槽，以及形成覆盖在介电层上和互连沟槽内的共形阻挡层。 通过从互连沟槽底部去除共形阻挡层而形成阻挡间隔物，并且在形成阻挡间隔物之后在互连沟槽内形成互连。 在邻近阻挡间隔物的电介质层中形成气隙沟槽，并且顶盖形成在互连和气隙沟槽上方，顶盖与气隙沟槽连接，以在气隙沟槽中产生气隙 。