公开(公告)号：US20140252557A1

公开(公告)日：2014-09-11

申请号：US13788719

申请日：2013-03-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L21/308 ,  H01L29/06

CPC classification number: H01L21/3083 ,  H01L29/0657 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

Abstract: Semiconductor device structures and methods for forming a semiconductor device are provided. In embodiments, one or more fins are provided, each of the one or more fins having a lower portion and an upper portion disposed on the lower portion. The lower portion is embedded in a first insulating material. The shape of the upper portion is at least one of a substantially triangular shape and a substantially rounded shape and a substantially trapezoidal shape. Furthermore, a layer of a second insulating material different from the first insulating material is formed on the upper portion.

Abstract translation: 提供了用于形成半导体器件的半导体器件结构和方法。 在实施例中，提供一个或多个翅片，所述一个或多个翅片中的每一个具有设置在下部的下部和上部。 下部嵌入第一绝缘材料中。 上部的形状是基本上三角形形状和大致圆形形状和大致梯形形状中的至少一个。 此外，在上部形成有与第一绝缘材料不同的第二绝缘材料层。

公开(公告)号：US20140252481A1

公开(公告)日：2014-09-11

申请号：US13792950

申请日：2013-03-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/41783 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/78 ,  H01L29/78603 ,  H01L29/78609 ,  H01L29/78696

Abstract: A semiconductor structure comprises a substrate and a transistor. The transistor comprises a raised source region and a raised drain region provided above the substrate, one or more elongated semiconductor lines, a gate electrode and a gate insulation layer. The one or more elongated semiconductor lines are connected between the raised source region and the raised drain region, wherein a longitudinal direction of each of the one or more elongated semiconductor lines extends substantially along a horizontal direction that is perpendicular to a thickness direction of the substrate. Each of the elongated semiconductor lines comprises a channel region. The gate electrode extends all around each of the channel regions of the one or more elongated semiconductor lines. The gate insulation layer is provided between each of the one or more elongated semiconductor lines and the gate electrode.

Abstract translation: 半导体结构包括衬底和晶体管。 晶体管包括设置在衬底上方的升高的源极区域和升高的漏极区域，一个或多个细长半导体管线，栅极电极和栅极绝缘层。 所述一个或多个细长半导体线连接在所述升高的源极区域和所述隆起的漏极区域之间，其中所述一个或多个细长半导体线路中的每一个的纵向方向基本上沿着垂直于所述衬底的厚度方向的水平方向延伸 。 每个细长半导体线包括沟道区。 栅电极围绕一个或多个细长半导体线路的每个沟道区域延伸。 栅极绝缘层设置在一个或多个细长半导体线路和栅电极中的每一个之间。

公开(公告)号：US20140151818A1

公开(公告)日：2014-06-05

申请号：US13689936

申请日：2012-11-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jan Hoentschel ,  Stefan Flachowsky

IPC: H01L21/28 ,  H01L29/78

CPC classification number: H01L21/265 ,  H01L21/28167 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/7833

Abstract: One illustrative method disclosed herein includes forming a gate insulation layer on a semiconducting substrate, performing an ion implantation process to implant a rare earth element into the gate insulation layer, and forming a silicon-containing gate electrode above the gate insulation layer comprising the implanted rare earth element. One illustrative device disclosed herein includes a gate insulation layer positioned on a semiconducting substrate, wherein the gate insulation layer is comprised of silicon dioxide and a rare earth element, and a silicon-containing gate electrode positioned on the gate insulation layer.

Abstract translation: 本文公开的一种示例性方法包括在半导体衬底上形成栅极绝缘层，执行离子注入工艺以将稀土元素注入到栅极绝缘层中，以及在栅极绝缘层上方形成含硅栅电极，该栅极绝缘层包括植入的稀有金属 地球元素 本文公开的一种说明性器件包括位于半导体衬底上的栅极绝缘层，其中栅极绝缘层由二氧化硅和稀土元素组成，并且位于栅极绝缘层上的含硅栅电极。

公开(公告)号：US20140117418A1

公开(公告)日：2014-05-01

申请号：US13663941

申请日：2012-10-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stefan Flachowsky ,  Ralf Illgen ,  Jan Hoentschel

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853

Abstract: Three-dimensional transistors may be formed on the basis of high mobility semiconductor materials, which may be provided locally restricted in the channel region by selective epitaxial growth processes without using a mask material for laterally confining the growing of the high mobility semiconductor material. That is, by controlling process parameters of the selective epitaxial growth process, the cross-sectional shape may be adjusted without requiring a mask material, thereby reducing overall process complexity and providing an additional degree of freedom for adjusting the transistor characteristics in terms of threshold voltage, drive current and electrostatic control of the channel region.

Abstract translation: 可以基于高迁移率半导体材料形成三维晶体管，高迁移率半导体材料可以通过选择性外延生长工艺局部限制在沟道区域中，而不用掩模材料横向地限制高迁移率半导体材料的生长。 也就是说，通过控制选择性外延生长工艺的工艺参数，可以调节横截面形状而不需要掩模材料，从而降低总体工艺复杂性，并提供用于根据阈值电压调整晶体管特性的附加自由度 ，驱动通道区域的电流和静电控制。

公开(公告)号：US20140113419A1

公开(公告)日：2014-04-24

申请号：US13654849

申请日：2012-10-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Thilo Scheiper ,  Jan Hoentschel ,  Markus Lenski ,  Rolf Stephan

IPC: H01L21/762 ,  H01L21/8238

CPC classification number: H01L21/823878 ,  H01L21/76224 ,  H01L21/823807 ,  Y02P80/30

Abstract: In one example, the method includes forming a plurality of isolation structures in a semiconducting substrate that define first and second active regions where first and second transistor devices, respectively, will be formed, forming a hard mask layer on a surface of the substrate above the first and second active regions, wherein the hard mask layer comprises at least one of carbon, fluorine, xenon or germanium ions, performing a first etching process to remove a portion of the hard mask layer and expose a surface of one of the first and second active regions, after performing the first etching process, forming a channel semiconductor material on the surface of the active region that was exposed by the first etching process, and after forming the channel semiconductor material, performing a second etching process to remove remaining portions of the hard mask layer that were not removed during the first etching process.

Abstract translation: 在一个示例中，该方法包括在半导体衬底中形成多个隔离结构，其限定第一和第二有源区，其中将分别形成第一和第二晶体管器件，在衬底的表面上形成硬掩模层， 第一和第二有源区，其中所述硬掩模层包括碳，氟，氙或锗离子中的至少一种，执行第一蚀刻工艺以去除所述硬掩模层的一部分并暴露所述第一和第二有源区中的一个的表面 活性区域，在进行第一蚀刻工艺之后，在通过第一蚀刻工艺曝光的有源区的表面上形成沟道半导体材料，并且在形成沟道半导体材料之后，执行第二蚀刻工艺以除去 硬掩模层，其在第一蚀刻工艺期间未被除去。

公开(公告)号：US10340380B2

公开(公告)日：2019-07-02

申请号：US15161399

申请日：2016-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/161

Abstract: A semiconductor device includes a plurality of spaced apart fins, a dielectric material layer positioned between each of the plurality of spaced apart fins, and a common gate structure positioned above the dielectric material layer and extending across the fins. A continuous merged semiconductor material region is positioned on each of the fins and above the dielectric material layer, is laterally spaced apart from the common gate structure, extends between and physically contacts the fins, has a first sidewall surface that faces toward the common gate structure, and has a second sidewall surface that is opposite of the first sidewall surface and faces away from the common gate structure. A stress-inducing material is positioned in a space defined by at least the first sidewall surface, opposing sidewall surfaces of an adjacent pair of fins, and an upper surface of the dielectric material layer.

公开(公告)号：US20190109192A1

公开(公告)日：2019-04-11

申请号：US15728679

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Damien Angot ,  Alban Zaka ,  Tom Herrmann ,  Venkata Naga Ranjith Kuma Nelluri ,  Jan Hoentschel ,  Lars Mueller-Meskamp ,  Martin Gerhardt

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/417 ,  H01L29/06 ,  H01L29/66

Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.

公开(公告)号：US09917087B2

公开(公告)日：2018-03-13

申请号：US13961554

申请日：2013-08-07

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Stefan Flachowksy ,  Juergen Faul ,  Jan Hoentschel

IPC: H01L21/8238 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823807

Abstract: Integrated circuits and methods of fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a bulk silicon substrate that is lightly-doped with a first dopant type divided into a first device region and a second device region, and a well region that is lightly-doped with a second dopant type formed in the second device region. The integrate circuit further includes heavily-doped source/drain extension regions of the first dopant type aligned to a first gate electrode structure and heavily-doped source/drain extension regions of the second dopant type aligned to a second gate electrode structure, and an intermediately-doped halo region of the second dopant type formed underneath the first gate electrode structure and an intermediately-doped halo regions of the first dopant type underneath the second gate electrode structure. Still further, the integrated circuit includes heavily-doped source/drain regions.

公开(公告)号：US20170345914A1

公开(公告)日：2017-11-30

申请号：US15648889

申请日：2017-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Elliot John Smith ,  Jan Hoentschel ,  Nigel Chan ,  Sven Beyer

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/423 ,  H01L29/417 ,  H01L29/06 ,  H01L27/12 ,  H01L21/84 ,  H01L21/308 ,  H01L29/78 ,  H01L21/306

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/41783 ,  H01L29/42324 ,  H01L29/4916 ,  H01L29/66484 ,  H01L29/7831

Abstract: A method includes forming a first material stack above a first transistor region, a second transistor region, and a dummy gate region of a semiconductor structure, the first material stack including a high-k material layer and a workfunction adjustment metal layer. The first material stack is patterned to remove a first portion of the first material stack from above the dummy gate region while leaving second portions of the first material stack above the first and second transistor regions. A gate electrode stack is formed above the first and second transistor regions and above the dummy gate region, and the gate electrode stack and the remaining second portions of the first material stack are patterned to form a first gate structure above the first transistor region, a second gate structure above the second transistor region, and a dummy gate structure above the dummy gate region.

公开(公告)号：US09608003B2

公开(公告)日：2017-03-28

申请号：US15193770

申请日：2016-06-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Peter Baars ,  Hans-Peter Moll ,  Jan Hoentschel

IPC: H01L29/49 ,  H01L27/12 ,  H01L21/308 ,  H01L21/321 ,  H01L21/762 ,  H01L21/84 ,  H01L27/06 ,  H01L49/02 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1207 ,  H01L21/308 ,  H01L21/3212 ,  H01L21/76224 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/0629 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/78 ,  H01L29/7838

Abstract: An integrated circuit product is disclosed including an SOI structure including a bulk semiconductor substrate, a buried insulation layer positioned on the bulk semiconductor substrate and a semiconductor layer positioned on the insulation layer, wherein, in a first region of the SOI structure, the semiconductor layer and the buried insulation layer are removed and, in a second region of the SOI structure, the semiconductor layer and the buried insulation layer are present above the bulk semiconductor substrate. The product further includes a semiconductor bulk device comprising a first gate structure positioned on the bulk semiconductor substrate in the first region and an SOI semiconductor device comprising a second gate structure positioned on the semiconductor layer in the second region, wherein the first and second gate structures have a final gate height substantially extending to a common height level above an upper surface of the bulk semiconductor substrate.