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    METHODS OF FORMING FEATURES HAVING DIFFERING PITCH SPACING AND CRITICAL DIMENSIONS
    21.
    发明申请
    METHODS OF FORMING FEATURES HAVING DIFFERING PITCH SPACING AND CRITICAL DIMENSIONS 有权
    形成具有不同间距和关键尺寸的特征的方法

    公开(公告)号：US20160163555A1

    公开(公告)日：2016-06-09

    申请号：US14676097

    申请日：2015-04-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Linus Jang ,  Ryan Ryoung-Han Kim

    IPC: H01L21/308 ,  H01L21/311 ,  H01L21/8234

    CPC classification number: H01L21/823456 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/823431

    Abstract: Methods of forming features having differing pitch spacing and critical dimensions are disclosed herein. One method includes forming an underlying layer of material above a semiconductor substrate. The method further includes forming a masking layer above the underlying layer of material. The masking layer includes features positioned above a first region of the substrate and features positioned above a second region of the substrate. The features have different pitch spacing and critical dimensions. The method further includes performing at least one etching process on the underlying layer of material through the masking layer.

    Abstract translation: 本文公开了形成具有不同间距间距和临界尺寸的特征的方法。 一种方法包括在半导体衬底上形成下层材料。 该方法还包括在材料的下层上形成掩模层。 掩模层包括位于衬底的第一区域上方的特征，以及位于衬底的第二区域之上的特征。 这些特征具有不同的间距和关键尺寸。 该方法还包括通过掩模层对材料的下层进行至少一个蚀刻工艺。

    SEMICONDUCTOR DEVICES WITH A LAYER OF MATERIAL HAVING A PLURALITY OF SOURCE/DRAIN TRENCHES
    22.
    发明申请
    SEMICONDUCTOR DEVICES WITH A LAYER OF MATERIAL HAVING A PLURALITY OF SOURCE/DRAIN TRENCHES 审中-公开
    具有多种源/排水沟的材料层的半导体器件

    公开(公告)号：US20150349053A1

    公开(公告)日：2015-12-03

    申请号：US14823226

    申请日：2015-08-11

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Ruilong Xie ,  William J. Taylor, JR. ,  Ryan Ryoung-Han Kim

    IPC: H01L29/06 ,  H01L29/51 ,  H01L29/08 ,  H01L29/78

    CPC classification number: H01L29/0653 ,  H01L29/0847 ,  H01L29/41791 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

    Abstract: One device disclosed herein includes an active region defined in a semiconductor substrate, a layer of material positioned above the semiconductor substrate, first and second laterally spaced-apart source/drain trenches defined in the layer of material above the active region, first and second conductive source/drain contact structures positioned within the first and second laterally spaced-apart source/drain trenches, respectively, a gate trench formed at least partially in the layer of material between the first and second laterally spaced-apart source/drain trenches in the layer of material, wherein portions of the layer of material remain positioned between the first and second laterally spaced-apart source/drain trenches and the gate trench, a gate structure positioned within the gate trench, and a gate cap layer positioned above the gate structure.

    Abstract translation: 本文公开的一种器件包括限定在半导体衬底中的有源区，位于半导体衬底上方的材料层，在有源区上方的材料层中限定的第一和第二横向间隔开的源极/漏极沟槽，第一和第二导电 源极/漏极接触结构分别位于第一和第二横向间隔开的源极/漏极沟槽内，栅极沟槽至少部分地形成在层中的第一和第二横向间隔开的源极/漏极沟槽之间的材料层中 的材料层，其中材料层的部分保持位于第一和第二横向间隔开的源极/漏极沟槽和栅极沟槽之间，位于栅极沟槽内的栅极结构以及位于栅极结构上方的栅极盖层。

    Methods of forming features having differing pitch spacing and critical dimensions
    28.
    发明授权
    Methods of forming features having differing pitch spacing and critical dimensions 有权
    形成具有不同间距间距和临界尺寸的特征的方法

    公开(公告)号：US09449835B2

    公开(公告)日：2016-09-20

    申请号：US14676097

    申请日：2015-04-01

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Linus Jang ,  Ryan Ryoung-Han Kim

    IPC: H01L21/00 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/311

    CPC classification number: H01L21/823456 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/823431

    Abstract: Methods of forming features having differing pitch spacing and critical dimensions are disclosed herein. One method includes forming an underlying layer of material above a semiconductor substrate. The method further includes forming a masking layer above the underlying layer of material. The masking layer includes features positioned above a first region of the substrate and features positioned above a second region of the substrate. The features have different pitch spacing and critical dimensions. The method further includes performing at least one etching process on the underlying layer of material through the masking layer.

    Abstract translation: 本文公开了形成具有不同间距间距和临界尺寸的特征的方法。 一种方法包括在半导体衬底上形成下层材料。 该方法还包括在材料的下层上形成掩模层。 掩模层包括位于衬底的第一区域上方的特征，以及位于衬底的第二区域之上的特征。 这些特征具有不同的间距和关键尺寸。 该方法还包括通过掩模层对材料的下层进行至少一个蚀刻工艺。

    METHODS FOR OPTICAL PROXIMITY CORRECTION IN THE DESIGN AND FABRICATION OF INTEGRATED CIRCUITS USING EXTREME ULTRAVIOLET LITHOGRAPHY
    29.
    发明申请
    METHODS FOR OPTICAL PROXIMITY CORRECTION IN THE DESIGN AND FABRICATION OF INTEGRATED CIRCUITS USING EXTREME ULTRAVIOLET LITHOGRAPHY 有权
    使用极端超紫外光刻技术在集成电路的设计和制造中进行光学近似校正的方法

    公开(公告)号：US20160162624A1

    公开(公告)日：2016-06-09

    申请号：US14685701

    申请日：2015-04-14

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Lei Sun ,  Wenhui Wang ,  Ryan Ryoung-Han Kim

    IPC: G06F17/50 ,  G03F1/22 ,  G03F1/70 ,  H01L21/027

    CPC classification number: G03F1/22 ,  G03F1/36 ,  G03F7/2045 ,  G06F17/5081 ,  H01L21/0274

    Abstract: A method of optical proximity correction (OPC) in extreme ultraviolet lithography (EUV) lithography includes providing a patterned layout design including first and second design polygons that correspond with the pre-pattern opening, wherein the first and second design polygons are separated by a separation distance, and correcting the patterned layout design using OPC by generating (1) a third polygon that has dimensions corresponding to a combination of the first and second design polygons and the separation distance and (2) and filled polygon within the third polygon, thereby generating an OPC-corrected patterned layout design. EUV photomasks may be manufactured from the OPC-corrected patterned layout design, and integrated circuits may be fabricated using such EUV photomasks.

    Abstract translation: 在极紫外光刻（EUV）光刻中的光学邻近校正（OPC）的方法包括提供图案化布局设计，其包括与预图案开口对应的第一和第二设计多边形，其中第一和第二设计多边形通过分离 距离，并且通过生成（1）具有对应于第一和第二设计多边形和分离距离的组合的尺寸的第三多边形以及（2）和第三多边形内的填充多边形来校正图案化布局设计，从而生成 OPC校正图案布局设计。 EUV光掩模可以由OPC校正的图案化布局设计制造，并且可以使用这种EUV光掩模来制造集成电路。

    METHODS OF FORMING PRODUCTS WITH FINFET SEMICONDUCTOR DEVICES WITHOUT REMOVING FINS IN CERTAIN AREAS OF THE PRODUCT
    30.
    发明申请
    METHODS OF FORMING PRODUCTS WITH FINFET SEMICONDUCTOR DEVICES WITHOUT REMOVING FINS IN CERTAIN AREAS OF THE PRODUCT 有权
    使用FINFET半导体器件形成产品的方法，无需在产品的某些领域中移除FINS

    公开(公告)号：US20160133726A1

    公开(公告)日：2016-05-12

    申请号：US14536026

    申请日：2014-11-07

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Min Gyu Sung ,  Ryan Ryoung-Han Kim

    IPC: H01L29/66 ,  H01L29/06 ,  H01L21/308 ,  H01L27/11

    CPC classification number: H01L29/66795 ,  H01L21/3086 ,  H01L27/1104 ,  H01L29/0642 ,  H01L29/66553 ,  H01L29/6681

    Abstract: One illustrative method disclosed herein includes, among other things, forming a first plurality of fins in the first region of the substrate, a second plurality of fins in the second region of the substrate, and a space in the substrate between two adjacent fins in the second region that corresponds to a first isolation region to be formed in the second region, forming a fin removal masking layer above the first and second regions of the substrate, wherein the fin removal masking layer has an opening positioned above at least a portion of at least one of the first plurality of fins, while masking all of the second plurality of fins in the second region and the space for the first isolation region, and performing an etching process through the first opening to remove the portions of the at least one of the first plurality of fins.

    Abstract translation: 本文公开的一种说明性方法包括在衬底的第一区域中形成第一多个鳍片，在衬底的第二区域中形成第二多个鳍片，以及在衬底中的两个相邻鳍片之间的空间 第二区域，其对应于将形成在第二区域中的第一隔离区域，在基板的第一和第二区域上方形成散热片去除掩模层，其中散热片移除掩模层具有位于至少一部分上方的开口 在第二区域中的所有第二多个散热片和第一隔离区域的空间中遮挡所有的第一多个散热片中的至少一个，并且通过第一开口执行蚀刻处理以去除至少一个 第一组多个翅片。

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