公开(公告)号：US20180233585A1

公开(公告)日：2018-08-16

申请号：US15945578

申请日：2018-04-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/40 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/76804 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/66 ,  H01L29/785

Abstract: Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged.

公开(公告)号：US09666717B2

公开(公告)日：2017-05-30

申请号：US14217691

申请日：2014-03-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Konstantin G. Korablev ,  Andy Chih-Hung Wei

IPC: H01L29/40 ,  H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/36 ,  H01L21/265

CPC classification number: H01L29/7851 ,  H01L21/26586 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/36 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/66795

Abstract: Approaches for altering the threshold voltage (e.g., to zero threshold voltage) in a fin-type field effect transistor (FinFET) device are provided. In embodiments of the invention, a first N+ region and a second N+ region are formed on a finned substrate that has a p-well construction. A region of the finned substrate located between the first N+ region and the second N+ region is doped with a negative implant species to form an n-well. The size and/or composition of this n-well region can be adjusted in view of the existing p-well construction of the substrate device to change the threshold voltage of the FinFET device (e.g., to yield a zero threshold voltage FinFET device).

公开(公告)号：US09368395B1

公开(公告)日：2016-06-14

申请号：US14270660

申请日：2014-05-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Mark A. Zaleski

IPC: H01L21/768 ,  H01L23/48

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76897 ,  H01L23/481 ,  H01L23/5283 ,  H01L23/5329 ,  H01L29/0649

Abstract: Provided are approaches for forming a self-aligned via and an air gap within a semiconductor device. Specifically, one approach produces a device having: a first metal line beneath a second metal line within an ultra low-k (ULK) dielectric, the first metal line connected to the second metal line by a first via; a dielectric capping layer formed over the second metal line; a third metal line within first and second via openings formed within a ULK fill material formed over the dielectric capping layer, wherein the third metal line within the first via opening extends to a top surface of the dielectric capping layer, and wherein the third metal line within the second via opening is connected to the second metal by a second via passing through the dielectric capping layer; and an air gap formed between the third metal line within the first and seconds via openings.

Abstract translation: 提供了用于在半导体器件内形成自对准通孔和气隙的方法。 具体地，一种方法产生一种器件，其具有：在超低k（ULK）电介质中的第二金属线下方的第一金属线，所述第一金属线通过第一通孔连接到所述第二金属线; 形成在所述第二金属线上的电介质覆盖层; 形成在形成在电介质覆盖层上的ULK填充材料内的第一和第二通孔内的第三金属线，其中第一通孔开口内的第三金属线延伸到介电覆盖层的顶表面，并且其中第三金属线 在第二通孔开口内通过穿过电介质盖层的第二通孔连接到第二金属; 以及形成在第一和第二通孔之间的第三金属线之间的气隙。

公开(公告)号：US20160093704A1

公开(公告)日：2016-03-31

申请号：US14963789

申请日：2015-12-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Mark A. Zaleski ,  Andy Chih-Hung Wei ,  Jason E. Stephens ,  Tuhin Guha Neogi ,  Guillaume Bouche

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/66

CPC classification number: H01L29/41758 ,  H01L21/8234 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/518 ,  H01L29/66348 ,  H01L29/66484 ,  H01L29/66545 ,  H01L29/66613 ,  H01L29/66621 ,  H01L29/66727 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.

公开(公告)号：US20160056104A1

公开(公告)日：2016-02-25

申请号：US14463803

申请日：2014-08-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Mark A. Zaleski

IPC: H01L23/528 ,  H01L21/02 ,  H01L21/768 ,  H01L21/3213 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76834 ,  H01L21/31144 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76832 ,  H01L21/76838 ,  H01L21/76897 ,  H01L23/52 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a method for self-aligned metal cuts in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. Spacers are formed on each Mx+1 sacrificial line. The gap between the spacers is used to determine the location and thickness of cuts to the Mx metal lines. This ensures that the Mx metal line cuts do not encroach on vias that interconnect the Mx and Mx+1 levels. It also allows for reduced limits in terms of via enclosure rules, which enables increased circuit density.

Abstract translation: 本发明的实施例提供了一种在线结构的后端中自对准金属切割的方法。 牺牲Mx + 1线形成在金属Mx线之上。 每个Mx + 1牺牲线上形成间隔。 使用间隔件之间的间隙来确定切割到Mx金属线的位置和厚度。 这样可确保Mx金属线切割不会侵入连接Mx和Mx + 1电平的通孔。 它还允许通过外壳规则降低限制，从而增加电路密度。

公开(公告)号：US20160056075A1

公开(公告)日：2016-02-25

申请号：US14463801

申请日：2014-08-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Mark A. Zaleski

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/311

CPC classification number: H01L23/5226 ,  H01L21/32139 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76877 ,  H01L21/76897 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide a method for cuts of sacrificial metal lines in a back end of line structure. Sacrificial Mx+1 lines are formed above metal Mx lines. A line cut lithography stack is deposited and patterned over the sacrificial Mx+1 lines and a cut cavity is formed. The cut cavity is filled with dielectric material. A selective etch process removes the sacrificial Mx+1 lines, preserving the dielectric that fills in the cut cavity. Precut metal lines are then formed by depositing metal where the sacrificial Mx+1 lines were removed. Thus embodiments of the present invention provide precut metal lines, and do not require metal cutting. By avoiding the need for metal cutting, the risks associated with metal cutting are avoided.

Abstract translation: 本发明的实施例提供了一种在线结构后端切割牺牲金属线的方法。 牺牲Mx + 1线形成在金属Mx线之上。 在牺牲Mx + 1线上沉积并图案化切割光刻叠层并形成切割腔。 切割腔填充有介电材料。 选择性蚀刻工艺去除牺牲Mx + 1线，保留填充切割腔的电介质。 然后通过沉积除去牺牲Mx + 1线的金属形成预切割的金属线。 因此，本发明的实施例提供预切割金属线，并且不需要金属切割。 通过避免金属切割的需要，避免与金属切割相关的风险。

公开(公告)号：US20160043081A1

公开(公告)日：2016-02-11

申请号：US14918012

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Dae-han Choi ,  Dae Geun Yang ,  Xiang Hu ,  Mariappan Hariharaputhiran

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L21/311 ,  H01L29/06 ,  H01L21/308 ,  H01L21/02

CPC classification number: H01L27/0886 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/30604 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/475 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/66795 ,  H01L29/785

Abstract: Embodiments of the present invention provide methods of removing fin portions from a finFET. At a starting point, a high-K dielectric layer is disposed on a substrate. A fin hardmask and lithography stack is deposited on the high-k dielectric. A fin hardmask is exposed, and a first portion of the fin hardmark is removed. The lithography stack is removed. A second portion of the fin hardmask is removed. Fins are formed. A gap fill dielectric is deposited and recessed.

公开(公告)号：US20150380250A1

公开(公告)日：2015-12-31

申请号：US14318901

申请日：2014-06-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy Chih-Hung Wei ,  Guillaume Bouche ,  Gabriel Padron Wells ,  Xiang Hu

IPC: H01L21/28 ,  H01L21/762 ,  H01L23/535 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L21/28008 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/535 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention provide an improved structure and method of contact formation. A cap nitride is removed from a gate in a region that is distanced from a fin. This facilitates reduced process steps, allowing the gate and the source/drain regions to be opened in the same process step. Extreme Ultraviolet Lithography (EUVL) may be used to pattern the resist to form the contacts.

Abstract translation: 本发明的实施例提供了改进的接触形成的结构和方法。 在与翅片间隔开的区域中，从栅极去除顶盖氮化物。 这有助于减少处理步骤，允许栅极和源极/漏极区域以相同的工艺步骤打开。 可以使用极紫外光刻（EUVL）来形成抗蚀剂以形成接触。

公开(公告)号：US20150340467A1

公开(公告)日：2015-11-26

申请号：US14282089

申请日：2014-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/76804 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/66 ,  H01L29/785

Abstract: Provided are approaches for forming merged gate and source/drain (S/D) contacts in a semiconductor device. Specifically, one approach provides a dielectric layer over a set of gate structures formed over a substrate; a set of source/drain (S/D) openings patterned in the dielectric layer between the gate structures; a fill material formed over the gate structures, including within the S/D openings; and a set of gate openings patterned over the gate structures, wherein a portion of the dielectric layer directly adjacent the fill material formed within one of the S/D openings is removed. The fill material is then removed, selective to the dielectric layer, and a metal material is deposited over the semiconductor device to form a set of gate contacts within the gate openings, and a set of S/D contacts within the S/D openings, wherein one of the gate contacts and one of the S/D contacts are merged.

Abstract translation: 提供了在半导体器件中形成合并的栅极和源极/漏极（S / D）触点的方法。 具体地，一种方法提供了在衬底上形成的一组栅极结构上的介电层; 在栅极结构之间的电介质层中图案化的一组源/漏（S / D）开口; 形成在栅极结构之上的填充材料，包括在S / D开口内; 以及在栅极结构上图案化的一组栅极开口，其中除去形成在S / D开口之一内的与填充材料直接相邻的电介质层的一部分。 然后去除填充材料，对电介质层有选择性，并且在半导体器件上沉积金属材料以在栅极开口内形成一组栅极触点，以及S / D开口内的一组S / D触点， 其中一个栅极触点和一个S / D触点被合并。

公开(公告)号：US20150340461A1

公开(公告)日：2015-11-26

申请号：US14282257

申请日：2014-05-20

Applicant: GLOBALFOUNDRIES Inc

Inventor： Andy Chih-Hung Wei ,  Dae G. Yang ,  Mariappan Hariharaputhiran ,  Jing Wan

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/785 ,  H01L21/28247 ,  H01L27/1104 ,  H01L29/4238 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/66 ,  H01L29/66545 ,  H01L29/66795

Abstract: Embodiments of the present invention provide a metal gate structure and method of formation. In the replacement metal gate (RMG) process flow, the gate cut process is performed after the metal gate is formed. This allows for a reduced margin between the end of the gate and an adjacent fin. It enables a thinner sacrificial layer on top of the dummy gate, since the gate cut step is deferred. The thinner sacrificial layer improves device quality by reducing the adverse effect of shadowing during implantation. Furthermore, in this process flow, the work function metal layer is terminated along the semiconductor substrate by a capping layer, which reduces undesirable shifts in threshold voltage that occurred in prior methods and structures.

Abstract translation: 本发明的实施例提供一种金属栅极结构和形成方法。 在替代金属栅极（RMG）工艺流程中，栅极切割工艺在金属栅极形成之后进行。 这允许在门的末端和相邻鳍之间减小边缘。 它能够在虚拟栅极顶部形成更薄的牺牲层，因为栅极切割步骤被推迟。 更薄的牺牲层通过减少植入期间阴影的不利影响来提高器件质量。 此外，在该工艺流程中，功函数金属层通过封盖层沿着半导体衬底终止，这降低了在现有方法和结构中发生的阈值电压的不期望的移动。