公开(公告)号：US20150194419A1

公开(公告)日：2015-07-09

申请号：US14148221

申请日：2014-01-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Andy Wei ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L29/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0296 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/861 ,  H01L29/866

Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

Abstract translation: 三维静电放电（ESD）半导体器件与三维非ESD半导体器件一起制造。 例如，ESD二极管和FinFET制造在相同的体半导体衬底上。 衬底合并技术用于衬底的ESD部分中以形成双宽度鳍片，其上可以使ESD器件更大以处理更多的电流。

公开(公告)号：US09040403B2

公开(公告)日：2015-05-26

申请号：US14244611

申请日：2014-04-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Thilo Scheiper ,  Stefan Flachowsky ,  Andy Wei

IPC: H01L21/3205 ,  H01L21/4763 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L21/76895 ,  H01L21/76897

Abstract: Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes forming a dummy gate structure including a dummy gate electrode having sidewalls and overlying a semiconductor substrate and first and second sidewall spacers on the sidewalls of the dummy gate electrode. The method includes removing the dummy gate electrode to form a trench bounded by the first and second sidewall spacers. The method removes an upper portion of the first sidewall spacer and deposits a layer of metal in the trench and over a remaining portion of the first sidewall spacer to form a gate electrode and an interconnect.

Abstract translation: 提供了用于制造包括门到活动触点的集成电路的方法。 一种方法包括形成虚拟栅极结构，其包括具有侧壁并覆盖半导体衬底的伪栅极电极以及虚设栅电极的侧壁上的第一和第二侧壁间隔物。 该方法包括去除伪栅电极以形成由第一和第二侧壁间隔物限定的沟槽。 该方法移除第一侧壁间隔物的上部，并将一层金属沉积在沟槽中并在第一侧壁间隔物的剩余部分上方形成栅电极和互连。

公开(公告)号：US09034767B1

公开(公告)日：2015-05-19

申请号：US14076386

申请日：2013-11-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang Hu ,  Dae-Han Choi ,  Dae Geun Yang ,  Taejoon Han ,  Andy Wei

IPC: H01L21/311 ,  H01L21/30 ,  H01L21/308

CPC classification number: H01L21/0337

Abstract: Mask pattern formation is facilitated by: providing a mask structure including at least one sacrificial spacing structure disposed above a substrate structure; disposing a spacer layer conformally over the mask structure; selectively removing the spacer layer, leaving, at least in part, sidewall spacers along sidewalls of the at least one sacrificial spacing structure, and providing at least one additional sacrificial spacer over the substrate structure, one additional sacrificial spacer of the at least one additional sacrificial spacer being disposed in set spaced relation to the at least one sacrificial spacing structure; and removing the at least one sacrificial spacing structure, leaving the sidewall spacers and the at least one additional sacrificial spacer over the substrate structure as part of a mask pattern.

Abstract translation: 通过以下方式促进掩模图案形成：提供掩模结构，其包括设置在基板结构上方的至少一个牺牲间隔结构; 将掩模层保形地设置在掩模结构上; 选择性地去除间隔层，至少部分地留下沿着至少一个牺牲间隔结构的侧壁的侧壁间隔物，并且在衬底结构上方提供至少一个额外的牺牲间隔物，该至少一个额外的牺牲隔离物 间隔件与所述至少一个牺牲间隔结构设置成间隔开的关系; 以及去除所述至少一个牺牲间隔结构，将所述侧壁间隔物和所述至少一个另外的牺牲隔离物留在所述衬底结构上作为掩模图案的一部分。

公开(公告)号：US20150021695A1

公开(公告)日：2015-01-22

申请号：US13944048

申请日：2013-07-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Zhenyu Hu ,  Richard J. Carter ,  Andy Wei ,  Qi Zhang ,  Sruthi Muralidharan ,  Amy L. Child

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/02

CPC classification number: H01L29/7848 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/24 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785

Abstract: Approaches for enabling uniform epitaxial (epi) growth in an epi junction area of a semiconductor device (e.g., a fin field effect transistor device) are provided. Specifically, a semiconductor device is provided including a dummy gate and a set of fin field effect transistors (FinFETs) formed over a substrate; a spacer layer formed over the dummy gate and each of the set of FinFETs; and an epi material formed within a set of recesses in the substrate, the set of recesses formed prior to removal of an epi block layer over the dummy gate.

Abstract translation: 提供了在半导体器件（例如，鳍式场效应晶体管器件）的外延连接区域中实现均匀外延（epi）生长的方法。 具体地说，提供了一种半导体器件，包括形成在衬底上的伪栅极和一组鳍状场效应晶体管（FinFET）; 形成在所述伪栅极和所述一组FinFET中的每一个上的间隔层; 以及形成在衬底中的一组凹部内的外延材料，该组凹陷在去除伪栅极之前的外延阻挡层之前形成。

公开(公告)号：US08846491B1

公开(公告)日：2014-09-30

申请号：US13921377

申请日：2013-06-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Daniel Pham ,  Zhenyu Hu ,  Andy Wei ,  Nicholas V. LiCausi

IPC: H01L21/76 ,  H01L29/78 ,  H01L21/762 ,  H01L21/02

CPC classification number: H01L29/785 ,  H01L21/02104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795

Abstract: Embodiments herein provide approaches for forming a diffusion break during a replacement metal gate process. Specifically, a semiconductor device is provided with a set of replacement metal gate (RMG) structures over a set of fins patterned from a substrate; a dielectric material over an epitaxial junction area; an opening formed between the set of RMG structures and through the set of fins, wherein the opening extends through the dielectric material, the expitaxial junction area, and into the substrate; and silicon nitride (SiN) deposited within the opening to form the diffusion break.

Abstract translation: 本文的实施例提供了在替换金属浇口工艺期间形成扩散断裂的方法。 具体而言，半导体器件在从衬底图案化的一组鳍片上设置有一组置换金属栅极（RMG）结构; 在外延结区上的电介质材料; 所述开口形成在所述一组RMG结构之间并且穿过所述一组翅片，其中所述开口延伸穿过所述电介质材料，所述外延结结区域并进入所述基板; 和沉积在开口内的氮化硅（SiN）以形成扩散断裂。

公开(公告)号：US20140027825A1

公开(公告)日：2014-01-30

申请号：US14039450

申请日：2013-09-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tim Baldauf ,  Andy Wei ,  Tom Herrmann ,  Stefan Flachowsky ,  Ralf Illgen

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886

Abstract: When forming sophisticated multiple gate transistors and planar transistors in a common manufacturing sequence, the threshold voltage characteristics of the multiple gate transistors may be intentionally “degraded” by selectively incorporating a dopant species into corner areas of the semiconductor fins, thereby obtaining a superior adaptation of the threshold voltage characteristics of multiple gate transistors and planar transistors. In advantageous embodiments, the incorporation of the dopant species may be accomplished by using the hard mask, which is also used for patterning the self-aligned semiconductor fins.

Abstract translation: 当在共同的制造顺序中形成复杂的多栅极晶体管和平面晶体管时，通过选择性地将掺杂剂物质结合到半导体鳍片的角区域中，可以有意地“降低”多个栅极晶体管的阈值电压特性，从而获得 多个栅极晶体管和平面晶体管的阈值电压特性。 在有利的实施方案中，可以通过使用硬掩模来实现掺杂物种的掺入，该硬掩模也用于图案化自对准半导体鳍片。

公开(公告)号：US09620587B2

公开(公告)日：2017-04-11

申请号：US14871181

申请日：2015-09-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Andy Wei ,  Mahadeva Iyer Natarajan

IPC: H01L27/02 ,  H01L29/06 ,  H01L21/306 ,  H01L21/308 ,  H01L29/417 ,  H01L29/45 ,  H01L29/861 ,  H01L29/866

CPC classification number: H01L29/0657 ,  H01L21/30604 ,  H01L21/308 ,  H01L21/3081 ,  H01L21/3086 ,  H01L27/0251 ,  H01L27/0255 ,  H01L27/0259 ,  H01L27/0296 ,  H01L29/41708 ,  H01L29/456 ,  H01L29/861 ,  H01L29/866

Abstract: Three-dimensional electrostatic discharge (ESD) semiconductor devices are fabricated together with three-dimensional non-ESD semiconductor devices. For example, an ESD diode and FinFET are fabricated on the same bulk semiconductor substrate. A spacer merger technique is used in the ESD portion of a substrate to create double-width fins on which the ESD devices can be made larger to handle more current.

公开(公告)号：US09601486B2

公开(公告)日：2017-03-21

申请号：US15156750

申请日：2016-05-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jagar Singh ,  Andy Wei ,  Mahadeva Iyer Natarajan ,  Manjunatha Prabhu ,  Anil Kumar

IPC: H01L27/02 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/088 ,  H01L27/027 ,  H01L29/0847 ,  H01L29/66477 ,  H01L29/66537 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/78 ,  H01L29/7835

Abstract: There is set forth herein a field effect transistor (FET) configured as an ESD protection device. In one embodiment, the FET can be configured to operate in a snapback operating mode. The FET can include a semiconductor substrate, a gate formed on the substrate and a dummy gate formed on the substrate spaced apart from the gate.

公开(公告)号：US09362165B1

公开(公告)日：2016-06-07

申请号：US14707443

申请日：2015-05-08

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Andy Wei ,  Sudharshanan Raghunathan

IPC: H01L23/48 ,  H01L21/02 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76897 ,  H01L23/528 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming 2D self-aligned vias before forming a subsequent metal layer and reducing capacitance of the resulting device and the resulting device are provided. Embodiments include forming dummy metal lines in a SiOC layer and extending in a first direction; replacing the dummy metal lines with metal lines, each metal line having a nitride cap; forming a softmask stack over the nitride cap and the SiOC layer; patterning a plurality of vias through the softmask stack down to the metal lines, the plurality of vias self-aligned along a second direction; removing the softmask stack; forming second dummy metal lines over the metal lines and extending in the second direction; forming a second SiOC layer between the dummy second metal lines on the SiOC layer; and replacing the dummy second metal lines with second metal lines, the second metal lines electrically connected to the metal lines through a via.

Abstract translation: 提供了在形成后续金属层之前形成2D自对准通孔并降低所得器件和所得器件的电容的方法。 实施例包括在SiOC层中形成虚拟金属线并沿第一方向延伸; 用金属线替代虚拟金属线，每条金属线都有氮化物盖; 在氮化物盖和SiOC层上形成软掩模堆叠; 通过所述软掩模堆叠将多个通孔图形化成金属线，所述多个通孔沿着第二方向自对准; 去除软掩码堆栈; 在金属线上形成第二虚拟金属线并在第二方向上延伸; 在SiOC层上的虚拟第二金属线之间形成第二SiOC层; 并且用第二金属线代替虚拟第二金属线，第二金属线通过通孔与金属线电连接。

公开(公告)号：US09196710B2

公开(公告)日：2015-11-24

申请号：US14177800

申请日：2014-02-11

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Andy Wei ,  Jin Ping Liu ,  Shao Ming Koh ,  Amaury Gendron

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/165

CPC classification number: H01L29/6681 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Integrated circuits with relaxed silicon and germanium fins and methods for fabricating such integrated circuits are provided. The method includes a forming a crystalline silicon and germanium composite layer overlying a crystalline silicon substrate, where a composite layer crystal lattice is relaxed. A fin is formed in the composite layer, and a gate is formed overlying the fin. A portion of the fin is removed on opposite sides of the gate to form a drain cavity and a source cavity, and a source and a drain are formed in the source cavity and drain cavity, respectively.

Abstract translation: 提供了具有松散硅和锗翅片的集成电路以及用于制造这种集成电路的方法。 该方法包括形成覆盖晶体硅衬底的晶体硅和锗复合层，其中复合层晶格被放宽。 在复合层中形成翅片，并且在翅片上形成栅极。 翅片的一部分在栅极的相对侧上被去除以形成漏腔和源腔，并且源极和漏极分别形成在源极腔和漏极腔中。