公开(公告)号：US20140264489A1

公开(公告)日：2014-09-18

申请号：US13840692

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hoong Shing WONG ,  Min-hwa CHI

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/66795 ,  H01L29/7848

Abstract: For the formation of a stressor on one or more of a source and drain defined on a fin of FINFET semiconductor structure, a method can be employed including performing selective epitaxial growth (SEG) on one or more of the source and drain defined on the fin, separating the fin from a bulk silicon substrate at one or more of the source and drain, and further performing SEG on one or more of the source and drain to form a wrap around epitaxial growth stressor that stresses a channel connecting the source and drain. The formed stressor can be formed so that the epitaxial growth material defining a wrap around configuration connects to the bulk substrate. The formed stressor can increase mobility in a channel connecting the defined source and drain.

Abstract translation: 为了在限定在FINFET半导体结构的鳍上的一个或多个源极和漏极上形成应力源，可以采用一种方法，包括在鳍上限定的一个或多个源极和漏极上执行选择性外延生长（SEG） 在源极和漏极中的一个或多个处将散热片与体硅衬底分离开，并且在源极和漏极之一上进一步执行SEG，以形成围绕外延生长应力的环绕，该外延生长应力应力连接源极和漏极的沟道。 形成的应力器可以形成为使得限定缠绕结构的外延生长材料连接到本体基板。 所形成的应力源可以增加连接限定的源极和漏极的通道中的迁移率。

公开(公告)号：US20180286873A1

公开(公告)日：2018-10-04

申请号：US15995896

申请日：2018-06-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L27/11 ,  H01L21/311 ,  H01L29/78 ,  H01L23/535 ,  H01L29/66 ,  H01L21/768

CPC classification number: H01L27/1104 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/535 ,  H01L27/11 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices for forming conductive paths between fins for contact-to-gate shorting. One method includes, for instance: obtaining wafer with a substrate, at least one fin, at least one hard mask, and an oxide layer; etching the oxide layer to reveal at least one of a portion of the hard masks; forming sacrificial pillars over the substrate; forming sacrificial gates, wherein at least one sacrificial gate contacts at least one sacrificial pillar; growing an epitaxial layer between the at least one sacrificial gate and the at least one sacrificial pillar; starting a RMG process on the sacrificial gates; etching to remove the sacrificial pillars and form pillar openings; and completing the RMG process to fill the pillar openings and the gate openings with a metal.

公开(公告)号：US20180277655A1

公开(公告)日：2018-09-27

申请号：US15994614

申请日：2018-05-31

Applicant: GLOBALFOUNDRIES INC.

Inventor： Srikanth Balaji SAMAVEDAN ,  Manfred ELLER ,  Min-hwa CHI ,  Hui ZANG

IPC: H01L29/66 ,  H01L21/308 ,  H01L21/306 ,  H01L29/06 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of reducing parasitic capacitance includes providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate with fin(s) thereon, the fin(s) having at least two dummy transistors integrated therewith and separated by a dielectric region, the dummy transistors including dummy gates with spacers and gate caps, the fin(s) having ends tucked by the dummy gates. The method further includes removing the dummy gates and gate caps, resulting in gate trenches, protecting area(s) of the structure during fabrication process(es) where source/drain parasitic capacitance may occur, and forming air-gaps at a bottom portion of unprotected gate trenches to reduce parasitic capacitance. The resulting semiconductor structure includes a semiconductor substrate with fin(s) thereon, FinFET(s) integral with the fin(s), the FinFET(s) including a gate electrode, a gate liner lining the gate electrode, and air-gap(s) in gate trench(es) of the FinFET(s), reducing parasitic capacitance by at least about 75 percent as compared to no air-gaps.

公开(公告)号：US20180158821A1

公开(公告)日：2018-06-07

申请号：US15370555

申请日：2016-12-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Changyong XIAO ,  Xusheng WU ,  Min-hwa CHI ,  Jie CHEN

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gate structures with low resistance and methods of manufacture. The structure includes: an nFET device formed in a first cavity having a first volume which is filled with conductive material; and a pFET device forming in a second cavity having a second volume greater than the first volume. The second volume being filled with the conductive material.

公开(公告)号：US20170365721A1

公开(公告)日：2017-12-21

申请号：US15674859

申请日：2017-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa CHI

IPC: H01L29/866 ,  H01L29/06 ,  H01L21/306 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/866 ,  H01L21/306 ,  H01L29/0684 ,  H01L29/0688 ,  H01L29/165 ,  H01L29/66106

Abstract: Diodes and fabrication methods thereof are presented. The diodes include, for instance: a first semiconductor region disposed at least partially within a substrate, the first semiconductor region having a first conductivity type; and a second semiconductor region disposed at least partially within the first semiconductor region, the second semiconductor region having a second conductivity type, wherein the first semiconductor region separates the second semiconductor region from the substrate. In one embodiment, the substrate and the first semiconductor region have U-shaped boundary. In a further embodiment, the first semiconductor region comprises an alloy of a first material and a second material, where the concentration of the second material varies from a maximum to a minimum, where the first semiconductor region adjacent to the second semiconductor region has the minimum of the concentration of the second material.

公开(公告)号：US20170338235A1

公开(公告)日：2017-11-23

申请号：US15160591

申请日：2016-05-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Manfred ELLER ,  Min-hwa CHI

IPC: H01L27/11 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/7856

Abstract: Circuit structures, such as inverters and static random access memories, and fabrication methods thereof are presented. The circuit structures include, for instance: a first transistor, the first transistor having a first channel region disposed above an isolation region; and a second transistor, the second transistor having a second channel region, the second channel region being laterally adjacent to the first channel region of the first transistor and vertically spaced apart therefrom by the isolation region thereof. In one embodiment, the first channel region and the isolation region of the first transistor are disposed above a substrate, and the substrate includes the second channel region of the second transistor. In another embodiment, the first transistor includes a fin structure extending from the substrate, and an upper portion of the fin structure includes the first channel region and a lower portion of the fin structure includes the isolation region.

公开(公告)号：US20170230004A1

公开(公告)日：2017-08-10

申请号：US15496049

申请日：2017-04-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yanxiang LIU ,  Min-hwa CHI

IPC: H03C3/14 ,  H01L29/08 ,  H01L29/06 ,  H03D7/12 ,  H01L29/66 ,  H01L29/78 ,  H01L27/088

CPC classification number: H03C3/145 ,  H01L27/088 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/66356 ,  H01L29/66568 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/78 ,  H01L29/7848 ,  H03C3/02 ,  H03C3/245 ,  H03D7/125

Abstract: Tunneling field effect transistors and fabrication methods thereof are provided, which include: an integrated circuit device which includes a circuit input configured to receive an input voltage and a circuit output configured to deliver an output current. The integrated circuit also includes a circuit element having at least one tunneling field effect transistor (TFET). The circuit element connects the circuit input to the circuit output and is characterized by a V-shaped current-voltage diagram. The V-shaped current-voltage diagram describes the relationship between the input voltage of the circuit input and the output current of the circuit output.

公开(公告)号：US20170213890A1

公开(公告)日：2017-07-27

申请号：US15482086

申请日：2017-04-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Jin Ping LIU ,  Min-hwa CHI

IPC: H01L29/165 ,  H01L29/08 ,  H01L29/737 ,  H01L29/78 ,  H01L21/265 ,  H01L29/66

CPC classification number: H01L29/165 ,  H01L21/26506 ,  H01L29/0821 ,  H01L29/0847 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/66636 ,  H01L29/732 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/7848

Abstract: Transistor structures and methods of fabricating transistor structures are provided. The methods include: fabricating a transistor structure at least partially within a substrate, the fabricating including: providing a cavity within the substrate; and forming a first portion and a second portion of the transistor structure at least partially within the cavity, the first portion being disposed at least partially between the substrate and the second portion, where the first portion inhibits diffusion of material from the second portion into the substrate. In one embodiment, the transistor structure is a field-effect transistor structure, and the first portion and the second portion include one of a source region or a drain region of the field-effect transistor structure. In another embodiment, the transistor structure is a bipolar junction transistor structure.

公开(公告)号：US20170033113A1

公开(公告)日：2017-02-02

申请号：US14814322

申请日：2015-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L27/108 ,  H01L29/66

CPC classification number: H01L27/10826 ,  H01L27/1085 ,  H01L27/10879 ,  H01L27/10888 ,  H01L28/90 ,  H01L29/66545

Abstract: A three-dimensional semiconductor device includes a semiconductor substrate, fin(s) coupled to the substrate and surrounded at a bottom portion thereof by isolation material, each fin including a source region, a drain region and a channel region therebetween, a first gate and spacers over a portion of each fin, and a second gate and spacers, the second gate encompassing a common end portion of each fin. The first gate and corresponding source and drain regions act as an access transistor, and the second gate and common end portion(s) of the fin(s) act as a storage capacitor, and a top surface of the second gate acts as a plate for the storage capacitor, when multiple cells are arranged in an array.

Abstract translation: 三维半导体器件包括：半导体衬底，耦合到衬底的鳍状物，并在其底部被隔离材料包围，每个散热片包括源极区，漏极区和它们之间的沟道区，第一栅极和 每个翅片的一部分上的间隔物，以及第二栅极和间隔物，第二栅极包围每个鳍片的共同端部。 第一栅极和相应的源极和漏极区域用作存取晶体管，并且鳍片的第二栅极和共同端部部分用作存储电容器，并且第二栅极的顶表面用作板 对于存储电容器，当多个单元被排列成阵列时。

公开(公告)号：US20160225849A1

公开(公告)日：2016-08-04

申请号：US14613983

申请日：2015-02-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chun Yu WONG ,  Min-hwa CHI ,  Ashish BARASKAR ,  Jagar SINGH

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/308 ,  H01L21/311 ,  H01L21/306 ,  H01L21/02

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3083 ,  H01L21/31116 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/78696

Abstract: Methods are presented for fabricating nanowire structures, such as one or more nanowire field effect transistors. The methods include, for instance: providing a substrate and forming a fin above the substrate so that the fin has a first sidewall including one or more elongate first sidewall protrusions and a second sidewall including one or more elongate second sidewall protrusions, with the one or more elongate second sidewall protrusions being substantially aligned with the one or more elongate first sidewall protrusions; and, anisotropically etching the fin with the elongate first sidewall protrusions and the elongate second sidewall protrusions to define the one or more nanowires. The etchant may be chosen to selectively etch along a pre-defined crystallographic plane, such as the (111) crystallographic plane, to form the nanowire structures.

Abstract translation: 提出了用于制造纳米线结构的方法，例如一个或多个纳米线场效应晶体管。 所述方法包括例如：提供衬底并在衬底上形成翅片，使得翅片具有包括一个或多个细长的第一侧壁突出部的第一侧壁和包括一个或多个细长的第二侧壁突出部的第二侧壁， 更细长的第二侧壁突起基本上与一个或多个细长的第一侧壁突起对准; 并且用细长的第一侧壁突起和细长的第二侧壁突起各向异性地蚀刻翅片以限定一个或多个纳米线。 可以选择蚀刻剂以沿着预定义的结晶平面（例如（111）晶面）选择性地蚀刻，以形成纳米线结构。