公开(公告)号：US20150294912A1

公开(公告)日：2015-10-15

申请号：US14725663

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L21/8234 ,  H01L21/308 ,  H01L29/78 ,  H01L21/3213 ,  H01L21/02 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

公开(公告)号：US20200227308A1

公开(公告)日：2020-07-16

申请号：US16246847

申请日：2019-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas V. LiCausi ,  Jeremy A. Wahl ,  Vimal K. Kamineni

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: Structures that include interconnects and methods for forming a structure that includes interconnects. A metallization level includes a metallization level having a first interconnect with a first top surface, a second interconnect with a second top surface, and a cavity with an entrance between the first interconnect and the second interconnect. A first dielectric layer includes a first section arranged on the first top surface of the first interconnect and a second section arranged on the second top surface of the second interconnect. The first section of the first dielectric layer is separated from the second section of the first dielectric layer by the entrance of the cavity. A second dielectric layer is arranged to surround the cavity and to close the entrance to the cavity in order to encapsulate an airgap inside the cavity.

公开(公告)号：US20200227307A1

公开(公告)日：2020-07-16

申请号：US16244387

申请日：2019-01-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas V. LiCausi

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L21/311 ,  H01L21/3105

Abstract: Structures that include interconnects and methods for forming a structure that includes interconnects. A metallization level has a first interconnect, a second interconnect, and a cavity with an entrance between the first interconnect and the second interconnect. A first dielectric layer includes a first section arranged on the first interconnect adjacent to the entrance of the cavity and a second section arranged on the second interconnect adjacent to the entrance of the cavity. A second dielectric layer is formed on the first section of the first dielectric layer and the second section of the first dielectric layer. The second dielectric layer extends from the first section of the first dielectric layer to the second section of the first dielectric layer and across the entrance to the cavity to close an airgap between the first interconnect and the second interconnect.

公开(公告)号：US20200144106A1

公开(公告)日：2020-05-07

申请号：US16177854

申请日：2018-11-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas V. LiCausi ,  Chanro Park ,  Ruilong Xie ,  Andre P. Labonte

IPC: H01L21/768

Abstract: An interconnect structure of an integrated circuit and a method of forming the same, the interconnect structure including: at least two metal lines laterally spaced from one another in a dielectric layer, the metal lines having a top surface below a top surface of the dielectric layer; a hardmask layer on an upper portion of sidewalls of the metal lines, the hardmask layer having a portion extending between the metal lines, the extending portion being below the top surface of the metal lines; and at least one fully aligned via on the top surface of a given metal line.

公开(公告)号：US09093302B2

公开(公告)日：2015-07-28

申请号：US14079159

申请日：2013-11-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Vimal K. Kamineni ,  Abner F. Bello ,  Nicholas V. LiCausi ,  Wenhui Wang ,  Michael Wedlake ,  Jason R. Cantone

IPC: H01L21/84 ,  H01L21/8238 ,  H01L27/092 ,  H01L27/12 ,  H01L27/108 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/785 ,  H01L21/02164 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/308 ,  H01L21/32133 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/10879 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7843 ,  H01L29/7846 ,  H01L2029/7858

Abstract: One method disclosed includes performing a selective etching process through a gate cavity to selectively remove a portion of a first semiconductor material relative to a second layer of a second semiconductor material and a substrate so as to thereby define a space between the second semiconducting material and the substrate, filling substantially all of the space with an insulating material so as to thereby define a substantially self-aligned channel isolation region positioned under at least what will become the channel region of the FinFET device.

Abstract translation: 所公开的一种方法包括通过栅极腔执行选择性蚀刻工艺，以相对于第二半导体材料和衬底的第二层选择性地去除第一半导体材料的一部分，从而限定第二半导体材料与第二半导体材料之间的空间 衬底，用绝缘材料填充基本上所有的空间，从而限定位于至少将成为FinFET器件的沟道区的至少自对准沟道隔离区。

公开(公告)号：US20150050792A1

公开(公告)日：2015-02-19

申请号：US13965258

申请日：2013-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Srikanth B. Samavedam ,  Zhenyu Hu ,  Andy Wei ,  Qi Zhang ,  Nicholas V. LiCausi ,  Daniel Pham

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224

Abstract: Methods for forming a narrow isolation region are disclosed. The narrow isolation region may serve as an extra narrow diffusion break, suitable for use in 3D FinFET technologies. A pad nitride layer is formed over a semiconductor substrate. A cavity is formed in the pad nitride layer. A conformal spacer liner is deposited in the cavity. An anisotropic etch process then forms a trench in the semiconductor substrate. The trench is narrow enough such that a dummy gate completely covers the trench. Epitaxial stressor regions may then be formed adjacent to the dummy gate. The trench is narrow enough such that there is a gap between the epitaxial stressor regions and the trench.

Abstract translation: 公开了形成窄隔离区域的方法。 狭窄的隔离区域可以用作非常窄的扩散断裂，适用于3D FinFET技术。 在半导体衬底上形成衬垫氮化物层。 在衬垫氮化物层中形成腔体。 在腔中沉积保形间隔衬垫。 然后，各向异性蚀刻工艺在半导体衬底中形成沟槽。 沟槽足够窄，使得虚拟栅极完全覆盖沟槽。 然后可以在与虚拟栅极相邻的位置形成外延应力区域。 沟槽足够窄，使得在外延应力区域和沟槽之间存在间隙。

公开(公告)号：US08889549B2

公开(公告)日：2014-11-18

申请号：US13766898

申请日：2013-02-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan Zhang ,  Nicholas V. LiCausi ,  Errol Todd Ryan

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76807 ,  H01L2221/1063

Abstract: One illustrative method disclosed herein includes performing a first etching process to define a via opening in a layer of insulating material, performing at least one process operation to form a sacrificial liner layer on the sidewalls of the via opening, performing a second etching process to define a trench in the layer of insulating material, wherein the sacrificial liner layer is exposed to the second etching process, after performing the second etching process, performing a third etching process to remove the sacrificial liner layer and, after performing the third etching process, forming a conductive structure in at least the via opening and the trench.

Abstract translation: 本文公开的一种说明性方法包括执行第一蚀刻工艺以在绝缘材料层中限定通孔开口，执行至少一个工艺操作以在通孔开口的侧壁上形成牺牲衬垫层，执行第二蚀刻工艺以界定 在所述绝缘材料层中的沟槽，其中所述牺牲衬垫层在进行所述第二蚀刻工艺之后暴露于所述第二蚀刻工艺，执行第三蚀刻工艺以去除所述牺牲衬垫层，并且在执行所述第三蚀刻工艺之后，形成 至少在通孔开口和沟槽中的导电结构。

公开(公告)号：US20140256064A1

公开(公告)日：2014-09-11

申请号：US13789966

申请日：2013-03-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： William J. Taylor, JR. ,  Nicholas V. LiCausi ,  Errol Todd Ryan

IPC: H01L21/02

CPC classification number: H01L21/31155 ,  H01L21/3105 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828

Abstract: One illustrative method disclosed herein includes providing a layer of a carbon-containing insulating material having a nominal carbon concentration, performing at least one process operation on the carbon-containing insulating material that results in the formation of a reduced-carbon-concentration region in the layer of carbon-containing insulating material, wherein the reduced-carbon-concentration region has a carbon concentration that is less than the nominal carbon concentration, performing a carbon-introduction process operation to introduce carbon atoms into at least the reduced-carbon-concentration region and thereby define a carbon-enhanced region having a carbon concentration that is greater than the carbon concentration of the reduced-carbon-concentration region and, after introducing the carbon atoms, performing a heating process on at least the carbon-enhanced region.

Abstract translation: 本文公开的一种说明性方法包括提供具有标称碳浓度的含碳绝缘材料的层，对含碳绝缘材料进行至少一个工艺操作，导致在所述含碳绝缘材料中形成还原碳浓度区域 含碳绝缘材料层，其中所述还原碳浓度区域的碳浓度小于标称碳浓度，进行碳引入工艺操作以将碳原子引入至少所述还原碳浓度区域 由此确定碳浓度大于还原碳浓度区域的碳浓度的碳增强区域，并且在引入碳原子之后，至少对碳增强区域进行加热处理。

公开(公告)号：US20140227849A1

公开(公告)日：2014-08-14

申请号：US13764839

申请日：2013-02-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas V. LiCausi ,  Jeremy A. Wahl

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775

Abstract: One illustrative method disclosed herein includes forming an initial nanowire structure having an initial cross-sectional size, performing a doping diffusion process to form an N-type doped region in the initial nanowire structure and performing an etching process to remove at least a portion of the doped region and thereby define a final nanowire structure having a final cross-sectional size, wherein the final cross-sectional size is smaller than the initial cross-sectional size.

Abstract translation: 本文公开的一种说明性方法包括形成具有初始横截面尺寸的初始纳米线结构，执行掺杂扩散工艺以在初始纳米线结构中形成N型掺杂区，并执行蚀刻工艺以去除至少一部分 从而限定具有最终横截面尺寸的最终纳米线结构，其中最终横截面尺寸小于初始横截面尺寸。

公开(公告)号：US10832944B2

公开(公告)日：2020-11-10

申请号：US16177854

申请日：2018-11-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas V. LiCausi ,  Chanro Park ,  Ruilong Xie ,  Andre P. Labonte

IPC: H01L21/768

Abstract: An interconnect structure of an integrated circuit and a method of forming the same, the interconnect structure including: at least two metal lines laterally spaced from one another in a dielectric layer, the metal lines having a top surface below a top surface of the dielectric layer; a hardmask layer on an upper portion of sidewalls of the metal lines, the hardmask layer having a portion extending between the metal lines, the extending portion being below the top surface of the metal lines; and at least one fully aligned via on the top surface of a given metal line.