公开(公告)号：US08846467B1

公开(公告)日：2014-09-30

申请号：US14021525

申请日：2013-09-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Roman Boschke ,  Stefan Flachowsky ,  Matthias Kessler

IPC: H01L21/8238

CPC classification number: H01L21/823835 ,  H01L21/823443

Abstract: A method for performing silicidation of a gate electrode is provided that includes forming both a first transistor with a first gate electrode covered by a cap layer and a semiconductor device on the same semiconductor substrate, forming an organic planarization layer (OPL) on the first transistor and the semiconductor device, back etching the OPL such that an upper surface of the OPL is positioned at a level that is below a level of an upper surface of the cap layer, forming a mask layer covering the semiconductor device without covering the first transistor, removing the cap layer while the back-etched OPL and the mask layer are present, and performing silicidation of the first gate electrode.

Abstract translation: 提供了一种执行栅极电极的硅化的方法，其包括在同一半导体衬底上形成第一晶体管与由盖层覆盖的第一栅电极和半导体器件，在第一晶体管上形成有机平坦化层（OPL） 和半导体器件，背面蚀刻OPL使得OPL的上表面位于低于帽层的上表面的水平的水平，形成覆盖半导体器件而不覆盖第一晶体管的掩模层， 在存在反蚀刻的OPL和掩模层的同时移除盖层，并且执行第一栅电极的硅化。

公开(公告)号：US20140269060A1

公开(公告)日：2014-09-18

申请号：US13834019

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Ricardo P. Mikalo ,  Stefan Flachowsky

IPC: H01L27/115 ,  G11C16/04

CPC classification number: H01L27/11521 ,  G11C16/0433 ,  G11C16/045 ,  H01L27/11558 ,  H01L29/0649 ,  H01L29/42324 ,  H01L29/4916

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided. In an exemplary embodiment, an integrated circuit includes a semiconductor substrate doped with a first conductivity-determining impurity. The semiconductor substrate has formed therein a first well doped with a second conductivity-determining impurity that is different from the first conductivity-determining impurity, a second well, formed within the first well, and doped with the first conductivity-determining impurity, and a third well spaced apart from the first and second wells and doped with the first conductivity-determining impurity. The integrated circuit further includes a floating gate structure formed over the semiconductor substrate. The floating gate structure includes a first gate element disposed over the second well and being separated from the second well with a dielectric layer, a second gate element disposed over the third well and being separated from the third well with the dielectric layer, and a conductive connector.

Abstract translation: 提供了用于制造集成电路的集成电路和方法。 在示例性实施例中，集成电路包括掺杂有第一导电性确定杂质的半导体衬底。 半导体衬底在其中形成有掺杂有与第一导电率确定杂质不同的第二导电率确定杂质的第一阱，形成在第一阱内的第二阱，并且掺杂有第一导电率确定杂质，以及 第三阱与第一阱和第二阱间隔开并掺杂有第一导电性确定杂质。 集成电路还包括形成在半导体衬底上的浮栅结构。 浮置栅极结构包括设置在第二阱上并与第二阱分离的第一栅极元件，其具有电介质层，第二栅极元件设置在第三阱上并与第三阱与介电层分离，并且导电 连接器。

公开(公告)号：US20140246696A1

公开(公告)日：2014-09-04

申请号：US13783547

申请日：2013-03-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stefan Flachowsky ,  Roman Boschke ,  Ralf Illgen

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: When forming sophisticated semiconductor devices including N-channel transistors with strain-inducing embedded source and drain semiconductor regions, N-channel transistor performance may be enhanced by selectively growing embedded pure silicon source and drain regions in cavities exposing the silicon/germanium layer of a Si/SiGe-substrate, wherein the silicon layer of the Si/SiGe-substrate may exhibit a strong bi-axial tensile strain. The bi-axial tensile strain may improve both electron and hole mobility.

Abstract translation: 当形成包括具有应变诱导嵌入式源极和漏极半导体区域的N沟道晶体管的复杂半导体器件时，可以通过选择性地生长暴露硅/锗层中的嵌入式纯硅源极和漏极区域来增强N沟道晶体管性能 / SiGe衬底，其中Si / SiGe衬底的硅层可能表现出强的双轴向拉伸应变。 双轴拉伸应变可以改善电子和空穴迁移率。

公开(公告)号：US08759922B2

公开(公告)日：2014-06-24

申请号：US13959237

申请日：2013-08-05

Applicant: GlobalFoundries Inc.

Inventor： Peter Javorka ,  Stefan Flachowsky ,  Thilo Scheiper

IPC: H01L29/78 ,  H01L27/01 ,  H01L21/28 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/66507 ,  H01L21/823814 ,  H01L21/823835 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7845

Abstract: Semiconductor devices are formed without full silicidation of the gates and with independent adjustment of silicides in the gates and source/drain regions. Embodiments include forming a gate on a substrate, forming a nitride cap on the gate, forming a source/drain region on each side of the gate, forming a first silicide in each source/drain region, removing the nitride cap subsequent to the formation of the first silicide, and forming a second silicide in the source/drain regions and in the gate, subsequent to removing the nitride cap. Embodiments include forming the first silicide by forming a first metal layer on the source/drain regions and performing a first RTA, and forming the second silicide by forming a second metal layer on the source/drain regions and on the gate and performing a second RTA.

Abstract translation: 半导体器件形成为没有栅极的完全硅化，并且独立调节栅极和源极/漏极区域中的硅化物。 实施例包括在基板上形成栅极，在栅极上形成氮化物盖，在栅极的每一侧形成源/漏区，在每个源/漏区中形成第一硅化物，在形成 第一硅化物，并且在去除氮化物盖之后，在源极/漏极区域和栅极中形成第二硅化物。 实施例包括通过在源极/漏极区上形成第一金属层并执行第一RTA来形成第一硅化物，以及通过在源极/漏极区域和栅极上形成第二金属层并执行第二RTA形成第二硅化物 。

公开(公告)号：US10340380B2

公开(公告)日：2019-07-02

申请号：US15161399

申请日：2016-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L29/161

Abstract: A semiconductor device includes a plurality of spaced apart fins, a dielectric material layer positioned between each of the plurality of spaced apart fins, and a common gate structure positioned above the dielectric material layer and extending across the fins. A continuous merged semiconductor material region is positioned on each of the fins and above the dielectric material layer, is laterally spaced apart from the common gate structure, extends between and physically contacts the fins, has a first sidewall surface that faces toward the common gate structure, and has a second sidewall surface that is opposite of the first sidewall surface and faces away from the common gate structure. A stress-inducing material is positioned in a space defined by at least the first sidewall surface, opposing sidewall surfaces of an adjacent pair of fins, and an upper surface of the dielectric material layer.

公开(公告)号：US09899417B2

公开(公告)日：2018-02-20

申请号：US15467305

申请日：2017-03-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Ralf Illgen

IPC: H01L27/12 ,  H01L21/265 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/3213 ,  H01L21/324 ,  H01L21/84 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L27/1207 ,  H01L21/26513 ,  H01L21/308 ,  H01L21/31051 ,  H01L21/32139 ,  H01L21/324 ,  H01L21/84 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/42364 ,  H01L29/42376 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/66689 ,  H01L29/7816 ,  H01L29/7833

Abstract: A semiconductor structure includes a semiconductor substrate, a layer of electrically insulating material above the semiconductor substrate, and a layer of semiconductor material above the layer of electrically insulating material. A first transistor includes a first source region, a first drain region, and a first channel region formed in the semiconductor substrate, a first gate insulation layer positioned above the first channel region, and an electrically conductive first gate electrode, wherein the first gate insulation layer includes a first portion of the electrically insulating material. A second transistor includes a second source region, a second drain region, and a second channel region formed in the layer of semiconductor material, a second gate insulation layer positioned above the second channel region, and an electrically conductive second gate electrode, wherein a second portion of the layer of electrically insulating material is positioned below the second channel region.

公开(公告)号：US09865608B2

公开(公告)日：2018-01-09

申请号：US15162151

申请日：2016-05-23

Applicant: GLOBALFOUNDRIES Inc. ,  Fraunhofer Gesellschaft zur Foerderung der angewandten Forschung e.V. ,  NaMLab gGmbH

Inventor： Johannes Mueller ,  Stefan Mueller ,  Stefan Flachowsky

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L29/51 ,  H01L27/11507

CPC classification number: H01L27/11507 ,  H01L21/28291 ,  H01L29/513 ,  H01L29/516 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6684 ,  H01L29/78391

Abstract: A method disclosed herein includes providing a semiconductor structure, the semiconductor structure comprising a semiconductor substrate and a gate stack, the gate stack comprising a gate insulation material over the substrate, a floating gate electrode material over the gate insulation material, a ferroelectric transistor dielectric over the floating gate electrode material and a top electrode material over the ferroelectric transistor dielectric, performing a first patterning process to remove portions of the top electrode material and the ferroelectric transistor dielectric and performing a second patterning process after the first patterning process to remove portions of the floating gate electrode material and the gate insulation material, wherein a projected area of an upper portion of the gate structure onto a plane that is perpendicular to a thickness direction of the substrate is smaller than a projected area of the lower portion of the gate structure onto the plane.

公开(公告)号：US20160118483A1

公开(公告)日：2016-04-28

申请号：US14522000

申请日：2014-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L29/66818 ,  H01L25/0657 ,  H01L29/0634 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78687 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides, in various aspects of the present disclosure, a semiconductor device which includes a semiconductor stack disposed over a surface of a substrate and a gate structure partially formed over an upper surface and two opposing sidewall surfaces of the semiconductor stack, wherein the semiconductor stack includes an alternating arrangement of at least two layers formed by a first semiconductor material and a second semiconductor material which is different from the first semiconductor material.

Abstract translation: 本公开在本公开的各个方面提供一种半导体器件，其包括设置在衬底的表面上的半导体堆叠和部分地形成在半导体堆叠的上表面和两个相对的侧壁表面上的栅极结构，其中， 半导体堆叠包括由第一半导体材料和与第一半导体材料不同的第二半导体材料形成的至少两层的交替布置。

公开(公告)号：US20160071886A1

公开(公告)日：2016-03-10

申请号：US14934369

申请日：2015-11-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Gerd Zschätzsch ,  Stefan Flachowsky ,  Dominic Thurmer

IPC: H01L27/12 ,  H01L29/08 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L27/1211 ,  H01L21/2254 ,  H01L21/823431 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66803 ,  H01L29/7834 ,  H01L29/785

Abstract: A semiconductor device includes a semiconductor material positioned above a substrate and a gate structure positioned above a surface of the semiconductor material, the gate structure covering a non-planar surface portion of the surface. A sidewall spacer is positioned adjacent to the gate structure and includes first dopants having one of an N-type and a P-type conductivity, wherein the sidewall spacer covers an entire sidewall surface of the gate structure and partially covers the surface of the semiconductor material. Source/drain extension regions that include the first dopants are positioned within the non-planar surface portion and in alignment with the sidewall spacer, wherein a concentration of the first dopants within a portion of the sidewall spacer proximate the non-planar surface portion substantially corresponds to a concentration of the first dopants within the source/drain extension regions proximate the non-planar surface portion.

Abstract translation: 半导体器件包括位于衬底上方的半导体材料和位于半导体材料表面之上的栅极结构，该栅极结构覆盖该表面的非平面表面部分。 侧壁间隔物定位成与栅极结构相邻，并且包括具有N型和P型导电体之一的第一掺杂剂，其中侧壁间隔物覆盖栅极结构的整个侧壁表面并且部分覆盖半导体材料的表面 。 包括第一掺杂剂的源极/漏极延伸区域位于非平面表面部分内并且与侧壁间隔物对准，其中邻近非平坦表面部分的侧壁间隔部分内的第一掺杂剂的浓度基本对应于 到靠近非平面表面部分的源极/漏极延伸区域内的第一掺杂剂的浓度。

公开(公告)号：US20160064515A1

公开(公告)日：2016-03-03

申请号：US14471660

申请日：2014-08-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Gerd Zschatzsch ,  Stefan Flachowsky ,  Jan Hoentschel

IPC: H01L29/66 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76885 ,  H01L23/485 ,  H01L29/517 ,  H01L29/66606 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One exemplary embodiment provides a method of making an integrated circuit. The method includes forming a dummy gate structure above a semiconductor substrate, etching an exposed semiconductor substrate outside the dummy gate structure, depositing silicon oxide over the dummy gate structure and the semiconductor substrate to form a silicon oxide layer, etching source and drain contact vias through the silicon oxide layer, implanting source and drain dopants through the source and drain contact vias, removing the dummy gate structure, forming a final gate structure, etching substantially all of the silicon oxide layer, and depositing an ultra low K dielectric to form an ultra low K dielectric layer.

Abstract translation: 一个示例性实施例提供了制造集成电路的方法。 该方法包括在半导体衬底之上形成虚拟栅极结构，蚀刻在虚拟栅极结构之外的暴露的半导体衬底，在虚拟栅极结构和半导体衬底上沉积氧化硅以形成氧化硅层，蚀刻源极和漏极接触通孔 氧化硅层，通过源极和漏极接触通孔注入源极和漏极掺杂剂，去除虚拟栅极结构，形成最终的栅极结构，蚀刻基本上所有的氧化硅层，以及沉积超低K电介质以形成超 低K电介质层。