公开(公告)号：US20160163702A1

公开(公告)日：2016-06-09

申请号：US14560049

申请日：2014-12-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Yue HU ,  Xin WANG ,  Yong Meng LEE ,  Wen-Pin PENG ,  Lun ZHAO ,  Wei-Hua TONG

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/45 ,  H01L29/417 ,  H01L29/06 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/02 ,  H01L21/311 ,  H01L21/285 ,  H01L29/165 ,  H01L29/08

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/31116 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/45 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: Methods for forming a trench silicide without gouging the silicon source/drain regions and the resulting devices are disclosed. Embodiments include forming first and second dummy gates, each with spacers at opposite sides thereof, on a substrate; forming eSiGe source/drain regions at opposite sides of the first dummy gate; forming raised source/drain regions at opposite sides of the second dummy gate; forming a silicon cap on each of the eSiGe and raised source/drain regions; forming an ILD over and between the first and second dummy gates; replacing the first and second dummy gates with first and second HKMG, respectively; forming a contact trench through the ILD into the silicon cap over each of the eSiGe and raised source/drain regions; and forming a silicide over the eSiGe and raised source/drain regions

Abstract translation: 公开了用于形成沟槽硅化物而不使硅源极/漏极区和所得到的器件气蚀的方法。 实施例包括在基板上形成第一和第二伪栅极，每个具有相对侧的间隔物; 在第一伪栅极的相对侧形成eSiGe源极/漏极区; 在所述第二虚拟栅极的相对侧形成凸起的源极/漏极区域; 在每个eSiGe和升高的源极/漏极区域上形成硅帽; 在第一和第二虚拟门之间和之间形成ILD; 分别用第一和第二HKMG代替第一和第二虚拟门; 在每个eSiGe和升高的源极/漏极区域上形成穿过ILD的接触沟槽进入硅帽; 并在eSiGe上形成硅化物并升高源极/漏极区域

公开(公告)号：US20160035723A1

公开(公告)日：2016-02-04

申请号：US14447193

申请日：2014-07-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Yanxiang LIU

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/45 ,  H01L21/66

CPC classification number: H01L22/14 ,  H01L21/823431 ,  H01L22/34 ,  H01L27/0886 ,  H01L29/41791 ,  H01L29/456 ,  H01L2225/06596

Abstract: The disclosure provides methods and devices for separately determining the channel resistance and the extension resistance of a FinFET. An exemplary embodiment includes forming first and second fins parallel to each other, forming at least one fin portion, connecting the first and second fins, forming a gate perpendicular to the first and second fins, over the at least one fin portion, forming a first source and a first drain over the first fin at opposite sides of the gate, and forming a second source and a second drain over the second fin, separate from the first source and drain, at opposite sides of the gate, wherein each of the first and second sources and first and second drains includes an extension region.

Abstract translation: 本公开提供用于单独确定FinFET的沟道电阻和扩展电阻的方法和装置。 一个示例性实施例包括形成彼此平行的第一和第二翅片，形成至少一个翅片部分，连接第一和第二翅片，在至少一个翅片部分上形成垂直于第一和第二翅片的门，形成第一 源极和位于栅极的相对侧的第一鳍片上的第一漏极，并且在栅极的相对侧处在第二鳍片上形成第二源极和第二漏极，该第二源极和第二漏极与第一源极和漏极分离，其中第一 并且第二源和第一和第二排水口包括延伸区域。

公开(公告)号：US20150318351A1

公开(公告)日：2015-11-05

申请号：US14267541

申请日：2014-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Xiang HU ,  Changyong XIAO ,  Wanxun HE

IPC: H01L29/06 ,  H01L29/161 ,  H01L21/02 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/308 ,  H01L29/16 ,  H01L27/088

CPC classification number: H01L29/161 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0657 ,  H01L29/7853

Abstract: A non-planar semiconductor structure includes raised semiconductor structures, e.g., fins, having epitaxial structures grown on top surfaces thereof, for example, epitaxial silicon naturally growing into a diamond shape. The surface area of the epitaxial structure may be increased by removing portion(s) thereof. The removal may create a multi-head (e.g., dual-head) epitaxial structure, together with the neck of the raised structure resembling a Y-shape. Raised structures that are not intended to include an epitaxial structure will be masked during epitaxial structure creation and modification. In addition, in order to have a uniform height, the filler material surrounding the raised structures is recessed around those to receive epitaxial structures.

Abstract translation: 非平面半导体结构包括凸起的半导体结构，例如具有在其顶表面上生长的外延结构的翅片，例如外延硅自然生长成菱形。 可以通过去除外延结构的部分来增加外延结构的表面积。 移除可以与类似于Y形的凸起结构的颈部一起形成多头（例如双头）外延结构。 在外延结构的制造和修改过程中，不会包含外延结构的凸起结构将被掩蔽。 此外，为了具有均匀的高度，围绕凸起结构的填充材料围绕接收外延结构的填充材料凹入。

公开(公告)号：US20150102826A1

公开(公告)日：2015-04-16

申请号：US14054040

申请日：2013-10-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Randy MANN ,  Sandeep PURI ,  Sonia GHOSH ,  Anuj GUPTA ,  Xusheng WU

IPC: G01B7/02 ,  G01R27/26

CPC classification number: H01L22/14 ,  G01B2210/56 ,  G06F17/5063 ,  G06F17/5068

Abstract: Methods and design structures for extraction of transistor channel width are disclosed. Embodiments may include determining effective channel widths of transistors of a plurality of integrated circuits as a function of drawn channel widths of the transistors, and determining a target channel width for a target transistor based on the effective channel widths.

Abstract translation: 公开了用于提取晶体管沟道宽度的方法和设计结构。 实施例可以包括根据晶体管的拉出沟道宽度确定多个集成电路的晶体管的有效沟道宽度，以及基于有效沟道宽度确定目标晶体管的目标沟道宽度。

公开(公告)号：US20190131452A1

公开(公告)日：2019-05-02

申请号：US15797380

申请日：2017-10-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ashish Kumar JHA ,  Hong YU ,  Xinyuan DOU ,  Xusheng WU ,  Dongil CHOI ,  Edmund K. BANGHART ,  Md Khaled HASSAN

IPC: H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L21/762 ,  H01L21/8238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to selective shallow trench isolation (STI) fill material for stress engineering in semiconductor structures and methods of manufacture. The structure includes a single diffusion break (SDB) region having at least one shallow trench isolation (STI) region with a stress fill material within a recess of the at least one STI region. The stress fill material imparts a stress on a gate structure adjacent to the at least one STI region.

公开(公告)号：US20190057899A1

公开(公告)日：2019-02-21

申请号：US15678229

申请日：2017-08-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou HUANG ,  Daniel JAEGER ,  Xusheng WU ,  Jinsheng GAO

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L21/02

CPC classification number: H01L21/76832 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76895 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

Abstract: A composite etch stop layer includes an oxide layer formed over a sacrificial gate structure and a nitride layer formed over the oxide layer. The oxide layer is disposed over only lower portions of the sacrificial gate structure while the nitride layer envelops the oxide layer and is disposed directly over a top surface of the sacrificial gate structure. Sensitivity of the nitride layer to oxidation, such as during the formation of an interlayer dielectric over the composite etch stop layer, is decreased by eliminating the oxide layer from upper portions of the sacrificial gate layer.

公开(公告)号：US20180190546A1

公开(公告)日：2018-07-05

申请号：US15393488

申请日：2016-12-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Haiting WANG

IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/66 ,  H01L27/092 ,  H01L29/49

CPC classification number: H01L21/823842 ,  H01L21/28088 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545

Abstract: A method for eliminating line voids during RMG processing and the resulting device are provided. Embodiments include forming dummy gates over PFET and NFET regions of a substrate, each dummy gate having spacers at opposite sides, and an ILD filling spaces between spacers; removing dummy gate material from the gates, forming a cavity between each pair of spacers; forming a high-k dielectric layer over the ILD and spacers and in the cavities; forming a metal capping layer over the high-k dielectric layer; forming a first work function metal layer over the metal capping layer; removing the first work function metal layer from the PFET region; forming a second work function metal layer over the metal capping layer in the PFET region and over the first work function metal layer in the NFET region; and forming a metal layer over the second work function metal layer, filling the cavities.

公开(公告)号：US20170371002A1

公开(公告)日：2017-12-28

申请号：US15190323

申请日：2016-06-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa CHI ,  Xusheng WU

IPC: G01R33/06 ,  H01L29/66 ,  H01L29/06 ,  H01L29/82 ,  H01L29/78

CPC classification number: G01R33/066 ,  G01R33/0058 ,  H01L29/0649 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/82

Abstract: Methods for forming an efficient and effective crossed-fins FinFET device for sensing and measuring magnetic fields and resulting devices are disclosed. Embodiments include forming first-fins, parallel to and spaced from each other, in a first direction on a substrate; forming second-fins, parallel to and spaced from each other on the substrate, in a same plane as the first fins and in a second direction perpendicular to and crossing the first-fins; forming a dummy gate with a spacer on each side over channel areas of the first and second fins; forming source/drain (S/D) regions at opposite ends of each first and second fin; forming an ILD over the fins and the dummy gate and planarizing to reveal the dummy gate; removing the dummy gate, forming a cavity; and forming a high-k/metal gate in the cavity.

公开(公告)号：US20170278925A1

公开(公告)日：2017-09-28

申请号：US15078247

申请日：2016-03-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jianwei PENG ,  Xusheng WU

IPC: H01L29/06 ,  H01L29/66 ,  H01L21/3105 ,  H01L29/78 ,  H01L21/308 ,  H01L21/306

CPC classification number: H01L29/0649 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/3105 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of introducing SDB material with a lower etch rate during a formation of a t-shape SDB STI structure are provided. Embodiments include providing an STI region in a Si substrate; forming a hardmask over the STI region and the Si substrate; forming a cavity through the hardmask over the STI region, the cavity having a width greater than a width of the STI region; depositing a SDB material in the cavity with an etch rate lower than HDP oxide to form a t-shaped SDB STI structure; and removing the hardmask.

公开(公告)号：US20170221888A1

公开(公告)日：2017-08-03

申请号：US15010189

申请日：2016-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Qizhi LIU ,  David HARAME ,  Renata Camillo-Castillo

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/324 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/324 ,  H01L21/823821 ,  H01L21/823892

Abstract: A method of making a semiconductor structure is provided including providing a plurality of fins on a semiconductor substrate; depositing a layer containing silicon dioxide on the plurality of fins and on a surface of the semiconductor substrate; depositing a photoresist layer on one or more but less than all of the plurality of fins; etching the layer of silicon dioxide off of one or more of the plurality of fins on which the photoresist layer had not been deposited; stripping the photoresist layer; depositing a layer of pure boron on one or more of the plurality of fins on which a photoresist had not been deposited; and depositing a silicon nitride liner step on the plurality of fins. A partial semiconductor device fabricated by said method is also provided.