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公开(公告)号：US20160343938A1
公开(公告)日：2016-11-24
申请号：US15114973
申请日：2014-03-07
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Gary Gibson , Richard Henze , Warren Jackson , Yoocharn Jeon
CPC classification number: H01L45/1293 , G11C13/004 , G11C13/0069 , G11C2013/0095 , H01L27/2418 , H01L45/04 , H01L45/08 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146
Abstract: A memristor device with a thermally-insulating cladding includes a first electrode, a second electrode, a memristor, and a thermally-insulating cladding. The memristor is coupled in electrical series between the first electrode and the second electrode. The thermally-insulating cladding surrounds at least a portion of the memristor.
Abstract translation: 具有绝热包层的回忆体装置包括第一电极，第二电极，忆阻器和绝热包层。 忆阻器以第一电极和第二电极之间的电气系列耦合。 绝热包层围绕至少一部分忆阻器。
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公开(公告)号：US20160343435A1
公开(公告)日：2016-11-24
申请号：US15112767
申请日：2014-01-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Yoocharn Jeon , Martin Foltin
IPC: G11C13/00
CPC classification number: G11C13/0035 , G11C13/0002 , G11C13/0007 , G11C13/0033 , G11C13/004 , G11C13/0069 , G11C13/0097 , G11C14/00
Abstract: A memristor memory is disclosed. In an example, a method of controlling a memristor memory includes operating the memristor memory in a volatile mode, wherein switching a state of a memristor cell is with a low writing load. The method also includes operating the same memristor memory in a non-volatile mode, wherein switching a state of the memristor cell is with a high writing load.
Abstract translation: 忆阻记忆体被公开。 在一个示例中，控制忆阻存储器的方法包括以易失性模式操作忆阻器存储器，其中，忆阻单元的状态切换具有低的写入负载。 该方法还包括在非易失性模式下操作相同的忆阻器存储器，其中开关忆阻器单元的状态具有高写入负载。
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公开(公告)号：US10049733B2
公开(公告)日：2018-08-14
申请号：US15500062
申请日：2014-10-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Naveen Muralimanohar , Erik Ordentlich , Yoocharn Jeon
IPC: G11C13/00
Abstract: A method to access two memory cells include determining a first cell current flowing through a first memory cell by subtracting a sneak current associated with the first memory cell from a first access current of the first bitline and determining a second cell current flowing through a second memory cell in the first bitline or a second bitline by subtracting the sneak current associated with the first memory cell from a second access current of the first bitline or the second bitline.
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公开(公告)号：US10049730B2
公开(公告)日：2018-08-14
申请号：US15320817
申请日：2014-07-31
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Yoocharn Jeon
Abstract: A crossbar array with shared drivers has a plurality of sets of row lines, a set of row drivers, a plurality of sets of column lines, a set of column drivers, and a plurality of memory cells. Each set of row lines has a plurality of row lines and is driven by a set of row drivers. Furthermore, each set of row lines intersects with a plurality of the sets of column lines. Likewise, each set of column lines has a plurality of column lines and is driven by a set of column drivers. Each set of column lines intersects with a plurality of the sets of row lines. Each memory cell is coupled between an intersection of a row line and a column line.
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25.发明授权公开(公告)号：US09934854B2
公开(公告)日：2018-04-03
申请号：US15500074
申请日：2014-11-14
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Yoocharn Jeon , James S. Ignowski
IPC: G11C13/00
CPC classification number: G11C13/004 , G06F13/1668 , G11C13/0002 , G11C13/0007 , G11C13/0023 , G11C27/024 , G11C2013/0045 , G11C2013/0054 , G11C2013/0057 , G11C2213/77
Abstract: A memory controller includes a voltage driver and a voltage comparator. The voltage driver applies a variable voltage to a selected line of a crossbar array to determine a first measured voltage that drives a first read current through a selected memory cell of the crossbar array. The voltage driver applies the variable voltage to the selected line to determine a second measured voltage that drives a second read current through the selected memory cell. The voltage comparator then determines a voltage difference between the first measured voltage and the second measured voltage and to compare the voltage difference with a reference voltage difference to determine a state of the selected memory cell. The crossbar array comprises a plurality of row lines, a plurality of column lines, and a plurality of memory cells. Each memory cell is coupled between a unique combination of one row line and one column line.
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Patent Agency Ranking
公开(公告)号：US09847378B2
公开(公告)日：2017-12-19
申请号：US15306125
申请日：2014-04-30
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Xia Sheng , Yoocharn Jeon , Jianhua Yang , Hans S. Cho , Richard H. Henze
CPC classification number: H01L27/2463 , G11C13/0002 , G11C13/003 , G11C2213/52 , G11C2213/71 , G11C2213/73 , H01L27/2481 , H01L27/249 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/1273 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1616 , H01L45/1675 , H01L45/1683
Abstract: A resistive memory device includes a conductor and a resistive memory stack in contact with the conductor. The resistive memory stack includes a multi-component electrode and a switching region. The multi-component electrode includes a base electrode having a surface, and an inert material electrode on the base electrode surface in a form of i) a thin layer, or ii) discontinuous nano-islands. A switching region is in contact with the conductor and with the inert material electrode when the inert material electrode is in the form of the thin layer; or the switching region is in contact with the conductor, with the inert material electrode, and with an oxidized portion of the base electrode when the inert material electrode is in the form of the discontinuous nano-islands.
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公开(公告)号：US20170053968A1
公开(公告)日：2017-02-23
申请号：US15306125
申请日：2014-04-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Xia Sheng , Yoocharn Jeon , Jianhua Yang , Hans S. Cho , Richard H. Henze
CPC classification number: H01L27/2463 , G11C13/0002 , G11C13/003 , G11C2213/52 , G11C2213/71 , G11C2213/73 , H01L27/2481 , H01L27/249 , H01L45/08 , H01L45/1233 , H01L45/1253 , H01L45/1273 , H01L45/145 , H01L45/146 , H01L45/16 , H01L45/1616 , H01L45/1675 , H01L45/1683
Abstract: A resistive memory device includes a conductor and a resistive memory stack in contact with the conductor. The resistive memory stack includes a multi-component electrode and a switching region. The multi-component electrode includes a base electrode having a surface, and an inert material electrode on the base electrode surface in a form of i) a thin layer, or ii) discontinuous nano-islands. A switching region is in contact with the conductor and with the inert material electrode when the inert material electrode is in the form of the thin layer; or the switching region is in contact with the conductor, with the inert material electrode, and with an oxidized portion of the base electrode when the inert material electrode is in the form of the discontinuous nano-islands.
Abstract translation: 电阻式存储器件包括与导体接触的导体和电阻式存储器堆叠。 电阻式存储器堆叠包括多组分电极和开关区域。 多组分电极包括具有表面的基极电极和基极电极表面上的惰性材料电极，其形式为i）薄层，或ii）不连续的纳米岛。 当惰性材料电极为薄层形式时，开关区域与导体和惰性材料电极接触; 或者当惰性材料电极为不连续的纳米岛的形式时，开关区域与惰性材料电极接触导体，并与基极的氧化部分接触。
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公开(公告)号：US20170040055A1
公开(公告)日：2017-02-09
申请号：US15305309
申请日：2014-04-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： David B. Fujii , Yoocharn Jeon , Siamak Tavallaei
CPC classification number: G11C13/004 , G11C11/56 , G11C11/5685 , G11C13/0002 , G11C13/0007 , G11C13/0069 , G11C2211/5641
Abstract: A multimodal memristor memory provides selectable or reconfigurable operation in a plurality of operational modes of a memristor. The multimodal memristor memory includes a memristor having a plurality of operational modes. The multimodal memristor memory further includes a reconfigurable interface driver to select an operational mode of the plurality of operational modes of the memristor. The memristor is to operate in the operational mode selected by the reconfigurable interface driver.
Abstract translation: 多模忆阻存储器在忆阻器的多个操作模式中提供可选择或可重新配置的操作。 多峰忆阻器存储器包括具有多个操作模式的忆阻器。 多模忆阻器存储器还包括可重配置接口驱动器，以选择忆阻器的多个操作模式的操作模式。 忆阻器将以由可重新配置的接口驱动程序选择的操作模式进行操作。
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公开(公告)号：US20160343433A1
公开(公告)日：2016-11-24
申请号：US15114760
申请日：2014-02-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Yoocharn Jeon
IPC: G11C13/00
CPC classification number: G11C13/004 , G11C2013/0054 , G11C2213/70 , G11C2213/77
Abstract: A method and a circuit for reading resistive states of memory elements within crossbar arrays includes a first crossbar array having first sets of row firms and column lines, with memory elements disposed at the intersections between the row lines and the column lines, a second crossbar array having second sets of row lines and column lines, with memory elements disposed at the intersections between the row lines and the column lines, and a comparator having a first input connected to the first crossbar array and a second input connected to the second crossbar array, wherein the first input is configured to receive a sense voltage from as select column in the first crossbar array and the second input is configured to receive a reference voltage from a corresponding select column in the second crossbar array.
Abstract translation: 用于读取交叉列阵列内的存储元件的电阻状态的方法和电路包括具有第一组行公司和列线的第一交叉开关阵列，其中存储元件设置在行线和列线之间的交点处，第二交叉列阵列 具有第二组行线和列线，其中存储元件设置在行线和列线之间的交点处;以及比较器，具有连接到第一交叉开关阵列的第一输入端和连接到第二交叉开关阵列的第二输入端， 其中所述第一输入被配置为从所述第一交叉开关阵列中的选择列接收感测电压，并且所述第二输入被配置为从所述第二交叉开关阵列中的相应选择列接收参考电压。
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公开(公告)号：US20160343432A1
公开(公告)日：2016-11-24
申请号：US15113914
申请日：2014-01-31
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Richard H. Henze , Naveen Muralimanohar , Yoocharn Jeon , Martin Foltin , Erik Ordentlich , Gregg B. Lesartre , R. Stanley Williams
IPC: G11C13/00 , H01L27/24 , H01L45/00 , H01L23/528
CPC classification number: G11C13/004 , G11C5/025 , G11C11/005 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/0069 , G11C2213/71 , G11C2213/72 , G11C2213/77 , G11C2213/79 , H01L23/528 , H01L27/2463 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/14 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147
Abstract: A non-volatile memory device with multiple latency tiers includes at least two crossbar memory arrays, each crossbar memory array comprising a number of memory cells, each memory cell connected to a word line and a bit line at a cross point. The crossbar memory arrays each have a different latency. The crossbar memory arrays are formed on a single die.
Abstract translation: 具有多个延迟层的非易失性存储器件包括至少两个交叉存储器阵列，每个横向存储器阵列包括多个存储器单元，每个存储器单元连接到字线和位于交叉点的位线。 交叉开关存储器阵列每个具有不同的延迟。 交叉开关存储器阵列形成在单个管芯上。
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