公开(公告)号：US08993453B1

公开(公告)日：2015-03-31

申请号：US13620071

申请日：2012-09-14

申请人： Krishnaswamy Ramkumar ,  Jeong Byun ,  Sagy Levy

发明人： Krishnaswamy Ramkumar ,  Jeong Byun ,  Sagy Levy

IPC分类号： H01L21/31

CPC分类号： H01L21/28282 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/4234 ,  H01L29/66833

摘要： A method for fabricating a nonvolatile charge trap memory device and the device are described. In one embodiment, the method includes providing a substrate in an oxidation chamber, wherein the substrate comprises a first exposed crystal plane and a second exposed crystal plane, and wherein the crystal orientation of the first exposed crystal plane is different from the crystal orientation of the second exposed crystal plane. The substrate is then subjected to a radical oxidation process to form a first portion of a dielectric layer on the first exposed crystal plane and a second portion of the dielectric layer on the second exposed crystal plane, wherein the thickness of the first portion of the dielectric layer is approximately equal to the thickness of the second portion of the dielectric layer.

摘要翻译： 描述了一种用于制造非易失性电荷陷阱存储器件及其装置的方法。 在一个实施例中，该方法包括在氧化室中提供衬底，其中衬底包括第一暴露的晶体面和第二暴露的晶面，并且其中第一暴露的晶面的晶体取向不同于 第二次暴露的晶面。 然后对基板进行自由基氧化处理，以在第一暴露的晶面上形成电介质层的第一部分，在第二暴露的晶面上形成电介质层的第二部分，其中电介质的第一部分的厚度 层大致等于电介质层的第二部分的厚度。

公开(公告)号：US08871595B2

公开(公告)日：2014-10-28

申请号：US13436878

申请日：2012-03-31

申请人： Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sagy Levy

发明人： Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sagy Levy

IPC分类号： H01L21/8239

CPC分类号： H01L29/7833 ,  B82Y10/00 ,  H01L21/28282 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7836 ,  H01L29/7843 ,  H01L29/792 ,  H01L29/7926

摘要： An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunneling layer; and forming a MOS device over a second region of the substrate.

摘要翻译： 描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。 通常，该方法包括：在衬底的第一区域中形成存储器件的通道，覆盖衬底表面的半导体材料，连接存储器件的源极和漏极的沟道; 在与所述通道的多个表面相邻的所述通道上形成电荷捕获电介质堆叠，其中所述电荷捕获电介质堆叠包括在隧道层上的电荷捕获层上的阻挡层; 以及在所述衬底的第二区域上形成MOS器件。

公开(公告)号：US08643124B2

公开(公告)日：2014-02-04

申请号：US13007533

申请日：2011-01-14

申请人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

发明人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

IPC分类号： H01L21/336

CPC分类号： H01L29/512 ,  C23C16/0272 ,  C23C16/308 ,  G11C16/0466 ,  H01L21/0214 ,  H01L21/02271 ,  H01L21/28282 ,  H01L21/3145 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

摘要： A semiconductor device including a silicon-oxide-oxynitride-oxide-silicon structure and methods of forming the same are provided. Generally, the structure comprises: a tunnel oxide layer on a surface of a substrate including silicon; a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which the stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which the stoichiometric composition of the second oxynitride layer results in it being trap dense; a blocking oxide layer on the second oxynitride layer; and a silicon containing gate layer on the blocking oxide layer. Other embodiments are also disclosed.

摘要翻译： 提供了包括氧化硅 - 氧氮化物 - 氧化物 - 硅结构的半导体器件及其形成方法。 通常，该结构包括：在包括硅的衬底的表面上的隧道氧化物层; 多层电荷存储层，其包括在所述隧道氧化物层上的富氧第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上不含杂质，并且所述第二氧氮化物层 第一氮氧化物层，其中第二氮氧化物层的化学计量组成导致其陷阱致密; 在第二氮氧化物层上的阻挡氧化物层; 以及在所述阻挡氧化物层上的含硅栅极层。 还公开了其他实施例。

公开(公告)号：US20090032863A1

公开(公告)日：2009-02-05

申请号：US12005813

申请日：2007-12-27

申请人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

发明人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L21/3143 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518

摘要： A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O2 and the reoxidation is performed with NO.

摘要翻译： 一种用于形成非易失性俘获电荷存储装置的隧道层的方法及其制成的制品。 该方法包括多次氧化和氮化操作，以提供比纯二氧化硅隧道层更高的介电常数，但是具有比在衬底界面处具有氮的隧穿层更少的氢和氮阱。 该方法提供了SONOS型设备中改进的存储器窗口。 在一个实施方案中，该方法包括氧化，氮化，再氧化和重新染色。 在一个实施方案中，首先用O 2进行氧化，并用NO进行再氧化。

公开(公告)号：US20080290400A1

公开(公告)日：2008-11-27

申请号：US11904506

申请日：2007-09-26

申请人： Fredrick B. Jenne ,  Sagy Levy

发明人： Fredrick B. Jenne ,  Sagy Levy

IPC分类号： H01L29/792 ,  H01L21/3205

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L21/3143 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518

摘要： Scaling a nonvolatile trapped-charge memory device and the article made thereby. In an embodiment, scaling includes multiple oxidation and nitridation operations to provide a tunneling layer with a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. In an embodiment, scaling includes forming a charge trapping layer with a non-homogenous oxynitride stoichiometry. In one embodiment the charge trapping layer includes a silicon-rich, oxygen-rich layer and a silicon-rich, oxygen-lean oxynitride layer on the silicon-rich, oxygen-rich layer. In an embodiment, the method for scaling includes a dilute wet oxidation to density a deposited blocking oxide and to oxidize a portion of the silicon-rich, oxygen-lean oxynitride layer.

摘要翻译： 缩放非易失性捕获电荷存储器件及其制成的制品。 在一个实施例中，缩放包括多次氧化和氮化操作，以提供具有高于纯二氧化硅隧道层的介电常数的隧道层，但是具有比在衬底界面处具有氮的隧穿层更少的氢和氮阱。 在一个实施例中，缩放包括形成具有非均匀氧氮化物化学计量的电荷俘获层。 在一个实施方案中，电荷俘获层包含富含硅的富氧层和在富硅的富氧层上的富含氧的贫氧氧氮化物层。 在一个实施方案中，缩放方法包括稀释湿氧化以密集沉积的阻塞氧化物并氧化一部分富含富含氧的氧氮化物层。

公开(公告)号：US20080290399A1

公开(公告)日：2008-11-27

申请号：US11904475

申请日：2007-09-26

申请人： Sagy Levy ,  Fredrick B. Jenne ,  Krishnaswamy Ramkumar

发明人： Sagy Levy ,  Fredrick B. Jenne ,  Krishnaswamy Ramkumar

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/66833

摘要： A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.

摘要翻译： 描述了非易失性电荷陷阱存储器件。 该器件包括具有沟道区和一对源极/漏极区的衬底。 栅极堆叠在沟道区域上方之间以及在一对源极/漏极区域之间的衬底之上。 栅极堆叠包括具有第一氘化层的多层电荷捕获区域。 多层电荷俘获区域还可以包括不含氘的电荷俘获层。

公开(公告)号：US20060110531A1

公开(公告)日：2006-05-25

申请号：US11115027

申请日：2005-04-26

申请人： Jane Chang ,  You-Sheng Lin ,  Avishai Kepten ,  Michael Sendler ,  Sagy Levy ,  Robin Bloom

发明人： Jane Chang ,  You-Sheng Lin ,  Avishai Kepten ,  Michael Sendler ,  Sagy Levy ,  Robin Bloom

IPC分类号： C23C16/00

CPC分类号： H01L21/0228 ,  C23C16/40 ,  C23C16/45525 ,  C23C16/45527 ,  C23C16/52 ,  H01L21/02148 ,  H01L21/02159 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31637 ,  H01L21/31641 ,  H01L21/31645

摘要： A method for depositing a high-k dielectric coating onto a substrate, such as a semiconductor wafer, is provided. The substrate is subjected to one or more reaction cycles. For instance, in a typical reaction cycle, the substrate is heated to a certain deposition temperature. Thereafter, in one embodiment, one or more reactive organo-metallic gas precursors are supplied to the reactor vessel. An oxidizing gas is also supplied to the substrate at a certain oxidizing temperature to oxidize and/or densify the layers. As a result, a metal oxide coating is formed that has a thickness equal to at least about one monolayer, and in some instances, two or more monolayers. The dielectric constant of the resulting metal oxide coating is often greater than about 4, and in some instance, is from about 10 to about 80.

公开(公告)号：US06451713B1

公开(公告)日：2002-09-17

申请号：US09836620

申请日：2001-04-17

申请人： Sing-Pin Tay ,  Yao Zhi Hu ,  Sagy Levy ,  Jeffrey Gelpey

发明人： Sing-Pin Tay ,  Yao Zhi Hu ,  Sagy Levy ,  Jeffrey Gelpey

IPC分类号： H01L2131

CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/31662 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/518

摘要： The oxynitride or oxide layer formed on a semiconductor substrate is pre-treated with UV-excited gas (such as chlorine or nitrogen) to improve the layer surface condition and increase the density of nucleation sites for subsequent silicon nitride deposition. The pre-treatment is shown to reduce the root mean square surface roughness of thinner silicon nitride films (with physical thicknesses below 36 Å, or even below 20 Å that are deposited on the oxynitride layer by chemical vapor deposition (CVD).

摘要翻译： 形成在半导体衬底上的氧氮化物或氧化物层用UV激发气体（如氯或氮）进行预处理，以改善层的表面状态，并提高后续氮化硅沉积的成核位置的密度。 预处理显示为减少通过化学气相沉积（CVD）沉积在氮氧化物层上的较薄的氮化硅膜（物理厚度低于或者甚至低于20埃）的均方根表面粗糙度。

公开(公告)号：US06191011B1

公开(公告)日：2001-02-20

申请号：US09167005

申请日：1998-09-28

申请人： Yitzhak Eric Gilboa ,  Benjamin Brosilow ,  Sagy Levy ,  Hedvi Spielberg ,  Itai Bransky

发明人： Yitzhak Eric Gilboa ,  Benjamin Brosilow ,  Sagy Levy ,  Hedvi Spielberg ,  Itai Bransky

IPC分类号： H01L2136

CPC分类号： H01L28/84 ,  C23C16/24 ,  C23C16/4401 ,  H01L21/02381 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639

摘要： Systems and methods are described for semiconductor wafer pretreatment. A method of increasing the selectivity of silicon deposition with regard to an underlying oxide layer during deposition of a silicon containing material by broadening a selective temperature of formation window for said silicon containing material by decreasing a lower temperature endpoint includes: providing a semiconductor wafer with the underlying oxide layer in a processing chamber; then pumping water from then processing chamber; and then depositing the silicon containing material on the semiconductor wafer. A step of seeding the semiconductor wafer can be conducted by exposing the semiconducotor wafer to a germanium containing gas. A chlorine containing precursor and/or hydrogen can be introduced into the processing chamber to increase the selectivity of the silicon containing material to the underlying oxide. The selective HSG temperature of formation window is widened. In addition, robustness with regard to changes in the reactor ambient and substrate condition, and selectivity with regard to underlying dielectric layers, are both improved.

摘要翻译： 描述了用于半导体晶片预处理的系统和方法。 通过通过降低较低温度端点拓宽所述含硅材料的形成窗口的选择温度来增加在沉积含硅材料期间相对于下面的氧化物层的硅沉积的选择性的方法包括：提供半导体晶片 处理室中的下面的氧化物层; 然后从处理室抽水; 然后将含硅材料沉积在半导体晶片上。 半导体晶片接合的步骤可以通过将半导体晶片暴露于含锗气体来进行。 可以将含氯前体和/或氢气引入处理室中以增加含硅材料对下面的氧化物的选择性。 形成窗口的选择性HSG温度加宽。 此外，关于反应器环境和衬底条件的变化以及关于底层电介质层的选择性的鲁棒性都得到改善。

公开(公告)号：US09449831B2

公开(公告)日：2016-09-20

申请号：US13436872

申请日：2012-03-31

申请人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

发明人： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

IPC分类号： H01L21/28 ,  G11C16/04 ,  H01L29/792 ,  B82Y10/00 ,  H01L29/423 ,  H01L29/78

CPC分类号： H01L29/66833 ,  B82Y10/00 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  H01L21/28282 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/4234 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/792 ,  H01L29/7926

摘要： An embodiment of a semiconductor memory device including a multi-layer charge storing layer and methods of forming the same are described. Generally, the device includes a channel formed from a semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device; a tunnel oxide layer overlying the channel; and a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which a stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which a stoichiometric composition of the second oxynitride layer results in it being trap dense. In one embodiment, the device comprises a non-planar transistor including a gate having multiple surfaces abutting the channel, and the gate comprises the tunnel oxide layer and the multi-layer charge storing layer.

摘要翻译： 描述了包括多层电荷存储层的半导体存储器件的实施例及其形成方法。 通常，该器件包括由半导体材料形成的沟道，该半导体材料覆盖连接存储器件的源极和漏极的衬底上的表面; 覆盖通道的隧道氧化物层; 以及多层电荷存储层，其在所述隧道氧化物层上包含富氧的第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上无陷阱，并且将贫氧的第二氮氧化物层置于 第一氧氮化物层，其中第二氧氮化物层的化学计量组成导致其陷阱致密。 在一个实施例中，该器件包括非平面晶体管，其包括具有邻接通道的多个表面的栅极，并且栅极包括隧道氧化物层和多层电荷存储层。