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    UV pretreatment process for ultra-thin oxynitride formation
    1.
    发明授权
    UV pretreatment process for ultra-thin oxynitride formation 失效
    用于超薄氧氮化物形成的UV预处理工艺

    公开(公告)号：US06451713B1

    公开(公告)日：2002-09-17

    申请号：US09836620

    申请日：2001-04-17

    申请人： Sing-Pin Tay ,  Yao Zhi Hu ,  Sagy Levy ,  Jeffrey Gelpey

    发明人： Sing-Pin Tay ,  Yao Zhi Hu ,  Sagy Levy ,  Jeffrey Gelpey

    IPC分类号： H01L2131

    CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L21/31662 ,  H01L21/3185 ,  H01L29/513 ,  H01L29/518

    摘要： The oxynitride or oxide layer formed on a semiconductor substrate is pre-treated with UV-excited gas (such as chlorine or nitrogen) to improve the layer surface condition and increase the density of nucleation sites for subsequent silicon nitride deposition. The pre-treatment is shown to reduce the root mean square surface roughness of thinner silicon nitride films (with physical thicknesses below 36 Å, or even below 20 Å that are deposited on the oxynitride layer by chemical vapor deposition (CVD).

    摘要翻译： 形成在半导体衬底上的氧氮化物或氧化物层用UV激发气体（如氯或氮）进行预处理，以改善层的表面状态，并提高后续氮化硅沉积的成核位置的密度。 预处理显示为减少通过化学气相沉积（CVD）沉积在氮氧化物层上的较薄的氮化硅膜（物理厚度低于或者甚至低于20埃）的均方根表面粗糙度。

    Nonvolatile charge trap memory device having a high dielectric constant blocking region
    3.
    发明授权
    Nonvolatile charge trap memory device having a high dielectric constant blocking region 有权
    具有高介电常数阻挡区域的非易失性电荷陷阱存储器件

    公开(公告)号：US09431549B2

    公开(公告)日：2016-08-30

    申请号：US13436875

    申请日：2012-03-31

    申请人： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

    发明人： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

    IPC分类号： H01L29/792 ,  B82Y10/00 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L27/115

    CPC分类号： H01L29/7923 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11578 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66833 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/792 ,  H01L29/7926

    摘要： An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.

    摘要翻译： 描述了非易失性电荷陷阱存储器件的实施例。 在一个实施例中，该装置包括一个通道，该沟道包括覆盖在电连接存储器件的第一扩散区和第二扩散区的衬底上的表面的硅以及与沟道的至少一部分相交并且覆盖的栅极堆，栅极 包括邻接通道的隧道氧化物的堆叠，邻接隧道氧化物的分裂电荷捕获区域和与分离的电荷捕获区域邻接的多层阻挡电介质。 分离电荷捕获区域包括第一电荷捕获层，其包含更接近隧道氧化物的氮化物，以及包含覆盖在第一电荷俘获层上的氮化物的第二电荷俘获层。 多层阻挡电介质至少包括高K电介质层。

    Radical oxidation process for fabricating a nonvolatile charge trap memory device
    4.
    发明授权
    Radical oxidation process for fabricating a nonvolatile charge trap memory device 有权
    用于制造非易失性电荷陷阱存储器件的自由基氧化工艺

    公开(公告)号：US08940645B2

    公开(公告)日：2015-01-27

    申请号：US13539458

    申请日：2012-07-01

    申请人： Krishnaswamy Ramkumar ,  Sagy Levy ,  Jeong Byun

    发明人： Krishnaswamy Ramkumar ,  Sagy Levy ,  Jeong Byun

    IPC分类号： H01L21/31

    CPC分类号： H01L29/7926 ,  B82Y10/00 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02238 ,  H01L21/02252 ,  H01L21/02271 ,  H01L21/02326 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28282 ,  H01L29/0669 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/775

    摘要： A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.

    摘要翻译： 描述了制造非易失性电荷陷阱存储器件的方法。 所述方法包括使衬底经受第一氧化工艺以形成覆盖多晶硅沟道的隧道氧化物层，以及在所述隧道氧化物层上形成多层电荷存储层，所述多层电荷存储层包含富氧的第一层，所述第一层包含氮化物，以及 在第一层上包含氮化物的贫氧第二层。 然后对衬底进行第二氧化处理以消耗第二层的一部分并形成覆盖多层电荷存储层的高温氧化物（HTO）层。 第一层的化学计量组成导致其基本上无陷阱，并且第二层的化学计量组成使其陷入致密。 第二氧化过程可以包括使用原位蒸汽发生的等离子体氧化过程或自由基氧化过程。

    Memory transistor with multiple charge storing layers and a high work function gate electrode
    5.
    发明授权
    Memory transistor with multiple charge storing layers and a high work function gate electrode 有权
    具有多个电荷存储层和高功函数栅电极的存储晶体管

    公开(公告)号：US08859374B1

    公开(公告)日：2014-10-14

    申请号：US13288919

    申请日：2011-11-03

    申请人： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

    发明人： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

    IPC分类号： H01L21/336

    CPC分类号： H01L29/513 ,  G11C16/0466 ,  G11C16/349 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02271 ,  H01L21/28035 ,  H01L21/28282 ,  H01L27/11573 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

    摘要： Semiconductor devices including non-volatile memory transistors and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the method comprises: (i) forming an oxide-nitride-oxide (ONO) dielectric stack on a surface of a semiconductor substrate in at least a first region in which a non-volatile memory transistor is to be formed, the ONO dielectric stack including a multi-layer charge storage layer; (ii) forming an oxide layer on the surface of the substrate in a second region in which a metal oxide semiconductor (MOS) logic transistor is to be formed; and (iii) forming a high work function gate electrode on a surface of the ONO dielectric stack. Other embodiments are also disclosed.

    摘要翻译： 提供包括非易失性存储晶体管的半导体器件及其制造方法以改善其性能。 在一个实施例中，该方法包括：（i）在其中将形成非易失性存储晶体管的至少第一区域中，在半导体衬底的表面上形成氧化物 - 氧化物 - 氧化物（ONO）电介质叠层， ONO电介质堆叠包括多层电荷存储层; （ii）在要形成金属氧化物半导体（MOS）逻辑晶体管的第二区域中在所述衬底的表面上形成氧化物层; 和（iii）在ONO电介质叠层的表面上形成高功函数栅电极。 还公开了其他实施例。

    Integration of non-volatile charge trap memory devices and logic CMOS devices
    6.
    发明授权
    Integration of non-volatile charge trap memory devices and logic CMOS devices 有权
    集成非易失性电荷陷阱存储器件和逻辑CMOS器件

    公开(公告)号：US08679927B2

    公开(公告)日：2014-03-25

    申请号：US12185751

    申请日：2008-08-04

    申请人： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy

    发明人： Krishnaswamy Ramkumar ,  Fredrick B. Jenne ,  Sagy Levy

    IPC分类号： H01L29/792

    CPC分类号： H01L29/7833 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7836 ,  H01L29/7843

    摘要： A semiconductor structure and method to form the same. The semiconductor structure includes a substrate having a non-volatile charge trap memory device disposed on a first region and a logic device disposed on a second region. A charge trap dielectric stack may be formed subsequent to forming wells and channels of the logic device. HF pre-cleans and SC1 cleans may be avoided to improve the quality of a blocking layer of the non-volatile charge trap memory device. The blocking layer may be thermally reoxidized or nitridized during a thermal oxidation or nitridation of a logic MOS gate insulator layer to densify the blocking layer. A multi-layered liner may be utilized to first offset a source and drain implant in a high voltage logic device and also block silicidation of the nonvolatile charge trap memory device.

    摘要翻译： 一种半导体结构及其形成方法。 半导体结构包括具有设置在第一区域上的非易失性电荷陷阱存储器件和设置在第二区域上的逻辑器件的衬底。 可以在形成逻辑器件的阱和通道之后形成电荷陷阱电介质叠层。 可以避免HF预清洗和SC1清洁，以提高非挥发性电荷陷阱存储器件的阻挡层的质量。 在逻辑MOS栅极绝缘体层的热氧化或氮化期间，阻挡层可以被热再氧化或氮化，以致密封阻挡层。 可以使用多层衬垫来首先在高压逻辑器件中偏置源极和漏极注入，并且还阻挡非易失性电荷陷阱存储器件的硅化。

    SONOS type stacks for nonvolatile change trap memory devices and methods to form the same
    7.
    发明授权
    SONOS type stacks for nonvolatile change trap memory devices and methods to form the same 有权
    用于非易失性变换陷阱存储器件的SONOS型堆栈及其形成方法

    公开(公告)号：US08163660B2

    公开(公告)日：2012-04-24

    申请号：US12413389

    申请日：2009-03-27

    申请人： Helmut Puchner ,  Igor Polishchuk ,  Sagy Levy

    发明人： Helmut Puchner ,  Igor Polishchuk ,  Sagy Levy

    IPC分类号： H01L21/31

    CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L29/4234 ,  H01L29/513 ,  H01L29/792

    摘要： A method for fabricating a nonvolatile charge trap memory device is described. The method includes forming a first oxide layer on a surface of a substrate. The first oxide layer is exposed to a first decoupled plasma nitridation process having a first bias. Subsequently, a charge-trapping layer is formed on the first oxide layer. The charge-trapping layer is exposed to an oxidation process and then to a second decoupled plasma nitridation process having a second, different, bias.

    摘要翻译： 描述了制造非易失性电荷陷阱存储器件的方法。 该方法包括在基板的表面上形成第一氧化物层。 第一氧化物层暴露于具有第一偏压的第一去耦等离子体氮化工艺。 随后，在第一氧化物层上形成电荷俘获层。 电荷捕获层暴露于氧化过程，然后暴露于具有第二不同偏压的第二去耦等离子体氮化工艺。

    Sequential deposition and anneal of a dielectic layer in a charge trapping memory device
    9.
    发明授权
    Sequential deposition and anneal of a dielectic layer in a charge trapping memory device 有权
    在电荷俘获存储器件中的介电层的顺序沉积和退火

    公开(公告)号：US08088683B2

    公开(公告)日：2012-01-03

    申请号：US12080166

    申请日：2008-03-31

    申请人： Krishnaswamy Ramkumar ,  Sagy Levy

    发明人： Krishnaswamy Ramkumar ,  Sagy Levy

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/28282 ,  H01L21/3145

    摘要： Deposition and anneal operations are iterated to break a deposition into a number of sequential deposition-anneal operations to reach a desired annealed dielectric layer thickness. In one particular embodiment, a two step anneal is performed including an NH3 or ND3 ambient followed by an N2O or NO ambient. In one embodiment, such a method is employed to form a dielectric layer having a stoichiometry attainable with only a deposition process but with a uniform material quality uncharacteristically high of a deposition process. In particular embodiments, sequential deposition-anneal operations provide an annealed first dielectric layer upon which a second dielectric layer may be left substantially non-annealed.

    摘要翻译： 重复沉积和退火操作以将沉积破坏成多个顺序的沉积退火操作以达到期望的退火介电层厚度。 在一个具体实施方案中，进行包括NH 3或ND 3环境，随后是N 2 O或NO环境的两步退火。 在一个实施例中，采用这种方法形成具有仅通过沉积工艺可获得的化学计量但具有均匀材料质量的电介质层，这在沉积过程中具有非常高的特性。 在特定实施例中，顺序沉积 - 退火操作提供退火的第一介电层，第二介电层可以在其上基本上保持不退火。