-
公开(公告)号：US10007517B2
公开(公告)日：2018-06-26
申请号：US15281280
申请日：2016-09-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Brent Buchanan , Le Zheng
CPC classification number: G06F9/3001 , G06F9/30 , G06N3/0635
Abstract: An example device may include multiply-accumulate circuitry and voltage-tracking modulator circuitry. The multiply-accumulate circuitry may be to increase and decrease an accumulation voltage held by an accumulator based on a number of input signals. The voltage-tracking modulator circuitry may be to generate an output signal based on the accumulation voltage, wherein the output signal is a continuous-time binary signal that tracks changes of the accumulation voltage by varying pulse widths of the output signal. The example device may be used as a neuron in a neural network.
-
公开(公告)号：US20180166133A1
公开(公告)日：2018-06-14
申请号：US15318718
申请日：2014-07-29
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Brent Buchanan
CPC classification number: G11C13/004 , G11C7/062 , G11C7/067 , G11C7/14 , G11C11/5678 , G11C13/0004 , G11C2207/063
Abstract: An example device in accordance with an aspect of the present disclosure includes a first module, a second module, and a third module. The first module is to compare an input current to a first reference current, and provide a first output. The second module is to compare the input current to a second reference current, and provide a second output. The third module is to compare the first output to the second output, and provide a third output indicative of a state associated with the input current.
-
公开(公告)号：US20180006449A1
公开(公告)日：2018-01-04
申请号：US15540192
申请日：2015-01-28
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Richard J. Auletta , Ning Ge
IPC: H02H9/04 , H01L21/8234 , H01L45/00 , H01L27/02 , H01L27/092 , G11C13/00
CPC classification number: H02H9/046 , G11C13/004 , G11C13/0097 , G11C2029/5002 , H01L21/823475 , H01L27/0266 , H01L27/0288 , H01L27/092 , H01L45/1608
Abstract: In the examples provided herein, an electrostatic discharge (ESD) recording circuit has a first memristive element coupled to a pin of an integrated circuit. The first memristive element switches from a first resistance to a second resistance when an ESD event occurs at the pin, and the first resistance is less than the second resistance. The ESD recording circuit also has shunting circuitry to shunt energy from an additional ESD event away from the first memristive element.
-
公开(公告)号：US09847132B1
公开(公告)日：2017-12-19
申请号：US15222234
申请日：2016-07-28
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Le Zheng , Brent Buchanan , John Paul Strachan
CPC classification number: G11C15/046 , G11C13/0069 , G11C2213/74 , G11C2213/79
Abstract: An example ternary content addressable memory. A bit cell of the memory may include first and second memristors, with a first terminal of the first memristor being connected to a first terminal of the second memristor via a node, a second terminal of the first memristor being switchably connected to a first data line, and a second terminal of the second memristor being switchably connected to a second data line. The bit cell may also include a match-line transistor that is connected between a first rail and a match line, with a gate of the match-line transistor being connected to the node.
-
公开(公告)号：US20170229171A1
公开(公告)日：2017-08-10
申请号：US15328269
申请日：2014-11-04
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Phillip David Misek , Brent Buchanan
IPC: G11C13/00
CPC classification number: G11C13/0023 , G11C13/0021 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C16/06 , G11C16/10 , G11C2013/0073 , G11C2213/77 , G11C2213/79
Abstract: Example implementations relate to memory array drivers. For example, a memory array includes a memory cell. The memory array also includes a bit line coupled to the memory cell and a word line coupled to the memory cell. The memory array further includes a first memory array driver having a first terminal and a second terminal. The first terminal is coupled to the bit line. The second terminal is coupled to the word line. The memory array further includes a second memory array driver having a third terminal and a fourth terminal. The third terminal is coupled to the bit line. The fourth terminal is coupled to the word line.
-
Patent Agency Ranking
公开(公告)号：US09691479B1
公开(公告)日：2017-06-27
申请号：US15142995
申请日：2016-04-29
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Emmanuelle J. Merced Grafals , Brent Buchanan , Le Zheng
CPC classification number: G11C13/0069 , G11C13/0002 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C2013/0076 , G11C2013/0088 , G11C2013/0092 , G11C2213/71 , G11C2213/74 , G11C2213/79
Abstract: A method of operating a plurality of memristive cells coupled as a memristor array includes initializing a first select line, and, in parallel for a number of memristor cells in the first select line, determining whether a level of conductance of the memristor cells in the first select line are within a tolerance of a reference conductance, and, in response to a determination that the level of conductance is not within the tolerance of the reference conductance, adjusting the level of conductance for the memristor cells in the first select line.
-
公开(公告)号：US20170062048A1
公开(公告)日：2017-03-02
申请号：US15307486
申请日：2014-04-30
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Ning Ge , Jianhua Yang , Adam L. Ghozeil , Brent Buchanan
IPC: G11C13/00
CPC classification number: G11C13/0038 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0064 , G11C13/0069 , G11C27/024 , G11C2013/0054 , G11C2013/0066 , G11C2013/0076 , G11C2013/0092
Abstract: A device for regulating memristor switching pulses is described. The device includes a voltage source to supply a voltage to a memristor. The device also includes a voltage detector to detect a memristor voltage. The memristor voltage is based on an initial resistance state of the memristor and the voltage supplied by the voltage source. The device also includes a comparator to compare the memristor voltage with a target voltage value for the memristor. The device also includes a feedback loop to indicate to a control switch when the memristor voltage is at least equal to the target voltage value. The device also includes a control switch to cut off the memristor from the voltage source when the memristor voltage is at least equal to the target voltage value.
Abstract translation: 描述了用于调节忆阻器切换脉冲的装置。 该装置包括用于向忆阻器提供电压的电压源。 该装置还包括检测忆阻器电压的电压检测器。 忆阻器电压基于忆阻器的初始电阻状态和由电压源提供的电压。 该器件还包括比较器，用于将忆阻器电压与忆阻器的目标电压值进行比较。 当存储器电压至少等于目标电压值时，该装置还包括反馈回路以向控制开关指示。 该装置还包括控制开关，当忆阻器电压至少等于目标电压值时，该开关用于从忆阻器与电压源切断。
-
公开(公告)号：US11315009B2
公开(公告)日：2022-04-26
申请号：US15449071
申请日：2017-03-03
Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
Inventor： Brent Buchanan , Miao Hu , John Paul Strachan
Abstract: An example electronic device includes a crossbar array, row driver circuitry, and column output circuits for each of the column lines of the crossbar array. The crossbar array may include row lines, column lines, and memristors that each are connected between one of the row lines and one of the column lines. The row driver circuitry may be to apply a plurality of analog voltages to a first node during a plurality of time periods, respectively, and, for each of the row lines, selectively connect the row line to the first node during one of the plurality of time periods based on a digital input vector. The column output circuits may each include: an integration capacitor, a switch that is controlled by an integration control signal, and current mirroring circuitry. The current mirroring circuitry may be to, when the switch is closed, flow an integration current to or from an electrode of the integration capacitor whose magnitude mirrors a current flowing on the corresponding column line. The integration control signal may be to close the switch for a specified amount of time during each of the plurality of time periods.
-
公开(公告)号：US10811065B2
公开(公告)日：2020-10-20
申请号：US15568458
申请日：2015-06-05
Applicant: Hewlett Packard Enterprise Development LP
Inventor： Brent Buchanan , Ning Ge , Richard James Auletta
Abstract: In the examples provided herein, an apparatus has a memristive element coupled to a pin of an integrated circuit, wherein the memristive element switches from a first resistance within a first range of resistance values to a second resistance within a second range of resistance values in response to an electrostatic discharge (ESD) event at the pin. The apparatus also has read circuitry coupled to the memristive element to determine whether a resistance of the memristive element is in the first or second range of resistance values, wherein the read circuitry includes a first transistor. Further, the coupling between the read circuitry and the memristive element does not include a direct path for current from the ESD event to a gate terminal of the first transistor.
-
公开(公告)号：US10770140B2
公开(公告)日：2020-09-08
申请号：US16065771
申请日：2016-01-27
Applicant: Hewlett Packard Enterprise Development LP
Inventor： John Paul Strachan , Brent Buchanan , Le Zheng
Abstract: The present disclosure provides a memristive array. The array includes a number of memristive devices. A memristive device is switchable between states and is to store information. The memristive array also includes a parallel reset control device coupled to the number of memristive devices in parallel. The parallel reset control device regulates a resetting operation for the number of memristive devices by regulating current flow through target memristive devices.
-
-
-
-
-
-
-
-
-
Search Results
83
records
(took 0.014 seconds)
