公开(公告)号：US06617660B2

公开(公告)日：2003-09-09

申请号：US09391507

申请日：1999-09-08

申请人： Shigeyuki Murai ,  Emi Fujii ,  Shigeharu Matsushita ,  Hisaaki Tominaga

发明人： Shigeyuki Murai ,  Emi Fujii ,  Shigeharu Matsushita ,  Hisaaki Tominaga

IPC分类号： H01L29095

CPC分类号： H01L29/66871 ,  H01L21/28587 ,  H01L29/42316 ,  H01L29/812

摘要： This invention has an objective to provide a field effect transistor semiconductor which has great adhesiveness between a gate metal and an insulating film defining a gate electrode end and to improve production yield thereof. The field effect transistor semiconductor of this invention comprises a source/drain electrode 6 positioned in a predetermined position in a GaAs substrate 1, a channel region provided in the GaAs substrate 1 and between the source/drain electrodes 6, a gate electrode 11 which is in schottky contact with a part of a channel region and is positioned between the source/drain electrodes 6, and an insulating film 7 which electrically insulates a surface of the GaAs substrate and the gate electrode 11 at both side surfaces of the gate electrode 11. The gate electrode 11 covers a part of the insulating film 7 and the surface of the GaAs substrate serving as the channel region, and a bottom metallic layer 8 contained in the gate electrode 11 is covered with a second metallic layer 9 which is highly adhesive to the insulating film 7.

摘要翻译： 本发明的目的是提供一种场效应晶体管半导体，其在栅极金属和限定栅电极端的绝缘膜之间具有很大的粘合性，并提高其生产成品率。本发明的场效应晶体管半导体包括源极/漏极 6位于GaAs衬底1中的预定位置，设置在GaAs衬底1中并在源/漏电极6之间的沟道区，与沟道区的一部分肖特基接触并位于 源极/漏极6以及绝缘膜7，其将栅极电极11的两个侧表面处的GaAs衬底的表面和栅极电极11电绝缘。栅电极11覆盖绝缘膜7的一部分，并且 作为沟道区的GaAs衬底的表面和包含在栅极11中的底部金属层8被第二个元件覆盖 与绝缘膜7高度粘合的层9。

公开(公告)号：US07440307B2

公开(公告)日：2008-10-21

申请号：US11584491

申请日：2006-10-23

申请人： Yoshiki Murayama ,  Shigeharu Matsushita

发明人： Yoshiki Murayama ,  Shigeharu Matsushita

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G11C11/223 ,  G11C11/5657

摘要： This memory comprises a bit line, a first word line and a second word line arranged to intersect with the bit line while holding the bit line therebetween and a first ferroelectric film and a second ferroelectric film, having capacitances different from each other, arranged between the bit line and the first word line and between the bit line and the second word line respectively at least on a region where the bit line and the first and second word lines intersect with each other. The bit line, the first word line and the first ferroelectric film constitute a first ferroelectric capacitor while the bit line, the second word line and the second ferroelectric film constitute a second ferroelectric capacitor, and the first ferroelectric capacitor and the second ferroelectric capacitor constitute a memory cell.

摘要翻译： 该存储器包括位线，第一字线和第二字线，其被布置成在保持位线之间与位线相交并且具有电容彼此不同的第一铁电体膜和第二铁电体膜，第一铁电体膜和第二铁电体膜布置在 至少在位线和第一和第二字线彼此相交的区域上分别位于第一字线和第一字线之间以及位线与第二字线之间。 位线，第一字线和第一铁电体膜构成第一铁电电容器，而位线，第二字线和第二铁电体膜构成第二铁电电容器，并且第一铁电电容器和第二铁电电容器构成 记忆单元

公开(公告)号：US06930906B2

公开(公告)日：2005-08-16

申请号：US10387869

申请日：2003-03-14

申请人： Shigeharu Matsushita ,  Yoh Takano ,  Satoru Sekine

发明人： Shigeharu Matsushita ,  Yoh Takano ,  Satoru Sekine

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A ferroelectric memory capable of improving disturbance resistance in a non-selected memory cell includes a bit line, a word line arranged to intersect with the bit line, and a memory cell, which is arranged between the bit line and the word line an includes a ferroelectric capacitor and a diode serially connected to the ferroelectric capacitor. Thus, when a voltage in a range hardly feeding a current to the diode is applied to a non-selected cell in data writing or data reading, substantially no voltage is applied to the ferroelectric capacitor.

摘要翻译： 能够提高未选择存储单元中的抗干扰性的铁电存储器包括位线，布置成与位线相交的字线以及布置在位线和字线a之间的存储单元，包括： 铁电电容器和串联连接到铁电电容器的二极管。 因此，当在数据写入或数据读取中向非选择单元施加难以向二极管供给电流的范围内的电压时，基本上不向铁电体电容器施加电压。

公开(公告)号：US6100547A

公开(公告)日：2000-08-08

申请号：US113386

申请日：1998-07-10

申请人： Shigeharu Matsushita

发明人： Shigeharu Matsushita

IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L21/285 ,  H01L21/338 ,  H01L29/47 ,  H01L29/812 ,  H01L27/085

CPC分类号： H01L21/28581 ,  H01L29/475 ,  H01L29/8128

摘要： A first electrode layer composed of Pt is formed on an operating layer, and a second electrode layer composed of a material which is different from Pt is formed on the operating layer so as to cover the first electrode layer. A buried electrode layer composed of Pt is formed in the operating layer under the first electrode layer. The first electrode layer, the second electrode layer and the buried electrode layer constitute a gate electrode.

摘要翻译： 在工作层上形成由Pt构成的第一电极层，在工作层上形成由与Pt不同的材料构成的第二电极层，以覆盖第一电极层。 在第一电极层下方的工作层中形成由Pt构成的掩埋电极层。 第一电极层，第二电极层和掩埋电极层构成栅电极。

公开(公告)号：US5751029A

公开(公告)日：1998-05-12

申请号：US651340

申请日：1996-05-17

申请人： Shigeharu Matsushita ,  Daijirou Inoue ,  Kohji Matsumura ,  Minoru Sawada ,  Yasoo Harada

发明人： Shigeharu Matsushita ,  Daijirou Inoue ,  Kohji Matsumura ,  Minoru Sawada ,  Yasoo Harada

IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/778 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/7784

摘要： An undoped Al.sub.0.22 Ga.sub.0.78 As layer, an undoped In.sub.0.2 Ga.sub.0.8 As electron-drifting layer, and an undoped GaAs electron-supplying layer are formed in order on a GaAs substrate. An impurity-doped layer .delta.-doped with Si donor is formed in the GaAs electron-supplying layer. An n-Al.sub.0.22 Ga.sub.0.78 As layer and n.sup.+ -GaAs cap layers are formed in order on the GaAs electron-supplying layer. A source electrode and a drain electrode are formed on the n.sup.+ -GaAs cap layers and a gate electrode is formed on the n-Al.sub.0.22 Ga.sub.0.78 As layer.

摘要翻译： 在GaAs衬底上依次形成未掺杂的Al0.22Ga0.78As层，未掺杂的In0.2Ga0.8As电子漂移层和未掺杂的GaAs电子供体层。 在GaAs电子供给层中形成掺杂有Si供体的杂质掺杂层δ。 在GaAs电子供给层上依次形成n-Al0.22Ga0.78As层和n + -GaAs覆盖层。 在n + -GaAs覆盖层上形成源电极和漏电极，在n-Al0.22Ga0.78As层上形成栅电极。

公开(公告)号：US5557141A

公开(公告)日：1996-09-17

申请号：US220542

申请日：1994-03-30

申请人： Yasoo Harada ,  Shigeharu Matsushita ,  Satoshi Terada ,  Emi Fujii ,  Takashi Kurose ,  Takayoshi Higashino ,  Takashi Yamada ,  Akihito Nagamatsu ,  Daijirou Inoue ,  Kouji Matsumura

发明人： Yasoo Harada ,  Shigeharu Matsushita ,  Satoshi Terada ,  Emi Fujii ,  Takashi Kurose ,  Takayoshi Higashino ,  Takashi Yamada ,  Akihito Nagamatsu ,  Daijirou Inoue ,  Kouji Matsumura

IPC分类号： H01L21/18 ,  H01L21/22 ,  H01L21/225 ,  H01L21/285 ,  H01L21/314 ,  H01L21/324 ,  H01L21/329 ,  H01L21/335 ,  H01L21/338 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/812 ,  H01L29/8605 ,  H01L23/58 ,  H01L29/00 ,  H01L29/06 ,  H01L31/0328

CPC分类号： B82Y10/00 ,  H01L21/22 ,  H01L21/2258 ,  H01L21/28587 ,  H01L21/28593 ,  H01L21/3144 ,  H01L21/3245 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/0891 ,  H01L29/1025 ,  H01L29/66075 ,  H01L29/66196 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66856 ,  H01L29/66871 ,  H01L29/66878 ,  H01L29/66977 ,  H01L29/775 ,  H01L29/7787 ,  H01L29/812 ,  H01L29/8122 ,  H01L29/8605 ,  Y10S148/034 ,  Y10S438/962

摘要： A group III-V compound semiconductor doped with an impurity, having an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed on a crystal of Group III-V compound semiconductor in which the silicon in the SiOx film is diffused into the Group III-V compound semiconductor, thereby forming a doped layer.

摘要翻译： 在III-V族化合物半导体的晶体上形成掺杂有杂质的III-V族化合物半导体的晶体，具有SiO x的未掺杂膜和防止V族原子扩散的膜（例如SiN膜） SiO x膜中的硅扩散到III-V族化合物半导体中，从而形成掺杂层。

公开(公告)号：US5350709A

公开(公告)日：1994-09-27

申请号：US75232

申请日：1993-06-10

申请人： Yasoo Harada ,  Shigeharu Matsushita ,  Satoshi Terada ,  Emi Fujii ,  Takashi Kurose ,  Takayoshi Higashino ,  Takashi Yamada ,  Akihito Nagamatsu ,  Daijirou Inoue ,  Kouji Matsumura

发明人： Yasoo Harada ,  Shigeharu Matsushita ,  Satoshi Terada ,  Emi Fujii ,  Takashi Kurose ,  Takayoshi Higashino ,  Takashi Yamada ,  Akihito Nagamatsu ,  Daijirou Inoue ,  Kouji Matsumura

IPC分类号： H01L21/18 ,  H01L21/22 ,  H01L21/225 ,  H01L21/285 ,  H01L21/314 ,  H01L21/324 ,  H01L21/329 ,  H01L21/335 ,  H01L21/338 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/66 ,  H01L29/775 ,  H01L29/778 ,  H01L29/812 ,  H01L29/8605

CPC分类号： B82Y10/00 ,  H01L21/22 ,  H01L21/2258 ,  H01L21/28587 ,  H01L21/28593 ,  H01L21/3144 ,  H01L21/3245 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/0891 ,  H01L29/1025 ,  H01L29/66075 ,  H01L29/66196 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66856 ,  H01L29/66871 ,  H01L29/66878 ,  H01L29/66977 ,  H01L29/775 ,  H01L29/7787 ,  H01L29/812 ,  H01L29/8122 ,  H01L29/8605 ,  Y10S148/034 ,  Y10S438/962

摘要： A method of doping a Group III-V compound semiconductor with an impurity, wherein after an undoped film of SiOx and a film for preventing the diffusion of Group V atoms (e.g., an SiN film) are formed in this order on a crystal of Group III-V compound semiconductor, the sample is subjected to at least one heat treatment to cause silicon in the SiOx film to diffuse into the Group III-V compound semiconductor, thereby forming a doped layer. Using this doped layer forming method, field-effect transistors, diodes, resistive layers, two-dimensional electron gas or one-dimensional quantum wires, zero-dimensional quantum boxes, electron wave interference devices, etc. are fabricated.

摘要翻译： 掺杂III-V族化合物半导体与杂质的方法，其中在未掺杂的SiOx膜和用于防止V族原子扩散的膜（例如，SiN膜）之后，依次形成在组的晶体上 III-V族化合物半导体，对该样品进行至少一次热处理以使SiOx膜中的硅扩散到III-V族化合物半导体中，从而形成掺杂层。 使用这种掺杂层形成方法，制造场效应晶体管，二极管，电阻层，二维电子气或一维量子线，零维量子箱，电子波干涉装置等。

公开(公告)号：US07247900B2

公开(公告)日：2007-07-24

申请号：US10631858

申请日：2003-08-01

申请人： Kazunari Honma ,  Shigeharu Matsushita

发明人： Kazunari Honma ,  Shigeharu Matsushita

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L28/60 ,  H01L21/02197 ,  H01L21/02282 ,  H01L21/31691 ,  H01L28/55

摘要： A dielectric device having excellent characteristics is provided. This dielectric device comprises such a first electrode layer that constituent elements located on its surface are terminated by halogen atoms and a dielectric film formed on the surface of the first electrode layer terminated by the halogen atoms. When the constituent elements for the first electrode layer located on the surface thereof are terminated by the halogen atoms in order to form a ferroelectric film having a bismuth layer structure, therefore, Bi constituting the ferroelectric film is inhibited from bonding to the constituent elements located on the surface of the first electrode layer.

摘要翻译： 提供了具有优异特性的电介质器件。 该电介质器件包括这样的第一电极层，其表面上的构成元件被卤素原子封端，并且形成在由卤素原子终止的第一电极层的表面上的电介质膜。 为了形成具有铋层结构的铁电体膜，为了形成具有铋层结构的铁电体膜而将位于其表面上的第一电极层的构成元件端接，因此，阻止构成铁电体膜的Bi与位于 第一电极层的表面。

公开(公告)号：US20070121365A1

公开(公告)日：2007-05-31

申请号：US11584491

申请日：2006-10-23

申请人： Yoshiki Murayama ,  Shigeharu Matsushita

发明人： Yoshiki Murayama ,  Shigeharu Matsushita

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G11C11/223 ,  G11C11/5657

摘要： This memory comprises a bit line, a first word line and a second word line arranged to intersect with the bit line while holding the bit line therebetween and a first ferroelectric film and a second ferroelectric film, having capacitances different from each other, arranged between the bit line and the first word line and between the bit line and the second word line respectively at least on a region where the bit line and the first and second word lines intersect with each other. The bit line, the first word line and the first ferroelectric film constitute a first ferroelectric capacitor while the bit line, the second word line and the second ferroelectric film constitute a second ferroelectric capacitor, and the first ferroelectric capacitor and the second ferroelectric capacitor constitute a memory cell.

摘要翻译： 该存储器包括位线，第一字线和第二字线，其被布置成在保持位线之间与位线相交并且具有电容彼此不同的第一铁电体膜和第二铁电体膜，第一铁电体膜和第二铁电体膜布置在 至少在位线和第一和第二字线彼此相交的区域上分别位于第一字线和第一字线之间以及位线与第二字线之间。 位线，第一字线和第一铁电体膜构成第一铁电电容器，而位线，第二字线和第二铁电体膜构成第二铁电电容器，并且第一铁电电容器和第二铁电电容器构成 记忆单元

公开(公告)号：US07167386B2

公开(公告)日：2007-01-23

申请号：US10304691

申请日：2002-11-27

申请人： Shigeharu Matsushita

发明人： Shigeharu Matsushita

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A ferroelectric memory capable of improving disturbance resistance in a non-selected cell by increasing the ratio between voltages applied to ferroelectric capacitors of a selected cell and the non-selected cell respectively is obtained. This ferroelectric memory comprises a bit line, a word line arranged to intersect with the bit line and a memory cell including a switching element arranged between the bit line and the word line and turned on with a threshold voltage having a substantially identical absolute value with respect to either of positive and negative voltage application directions and a ferroelectric capacitor arranged between the bit line and the word line and serially connected to the switching element.

摘要翻译： 获得能够通过增加施加到所选择的单元的铁电电容器和非选择单元的电压之间的比率来提高未选择单元中的抗干扰性的铁电存储器。 该铁电存储器包括位线，布置成与位线相交的字线和包括布置在位线和字线之间的开关元件的存储单元，并且以相对于绝对值基本相同的阈值电压而导通 布置在位线和字线之间的串联连接到开关元件的强电介质电容器。