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    Semiconductor memory device having improved controlling function for data buses
    21.
    发明授权
    Semiconductor memory device having improved controlling function for data buses 失效
    具有改善数据总线控制功能的半导体存储器件

    公开(公告)号：US5278788A

    公开(公告)日：1994-01-11

    申请号：US665865

    申请日：1991-03-07

    申请人： Hidenori Nomura

    发明人： Hidenori Nomura

    IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C11/409 ,  G11C7/00

    CPC分类号： G11C7/1048

    摘要： In a semiconductor memory device wherein a difference in potential of two data buses is increased during a write mode and is reduced during a read mode, a write/restoring circuit is provided for carrying out a write operation which increases the difference in potential between the data buses and a restoring operation which reduces the increased difference in potential of the data buses to carry out a read operation after the write operation in accordance with a common write control signal using common output transistors.

    摘要翻译： 在写入模式期间两个数据总线的电位差增加并且在读取模式期间减小的半导体存储器件中，提供写入/恢复电路用于执行增加数据之间的电位差的写入操作 总线和恢复操作，其减少数据总线的电位差增加，以便根据使用公共输出晶体管的公共写入控制信号在写入操作之后执行读取操作。

    Semiconductor memory device having data bus reset circuit
    22.
    发明授权
    Semiconductor memory device having data bus reset circuit 失效
    具有数据总线复位电路的半导体存储器件

    公开(公告)号：US4821232A

    公开(公告)日：1989-04-11

    申请号：US97556

    申请日：1987-09-16

    申请人： Masao Nakano ,  Tsuyoshi Ohira ,  Hirohiko Mochizuki ,  Yukinori Kodama ,  Hidenori Nomura

    发明人： Masao Nakano ,  Tsuyoshi Ohira ,  Hirohiko Mochizuki ,  Yukinori Kodama ,  Hidenori Nomura

    IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C7/20 ,  G11C13/00 ,  G11C11/40

    CPC分类号： G11C7/20 ,  G11C7/1048

    摘要： A semiconductor memory device comprises a memory cell array comprising a plurality of memory cells arranged in a matrix arrangement, a sense amplifier, operatively connected to the memory cell array, amplifying a signal read out from one of the memory cells and having a pair of output terminals for outputting a complementary signal, a pair of data buses for transferring the complementary signal, a transfer gate for connecting the pair of output terminals to the pair of data buses responsive to a read operation, a data output buffer connected to the pair of data buses for outputting an output signal, and a reset circuit for resetting the pair of data buses to a predetermined voltage before each read operation responsive to a reset clock signal. The reset circuit comprises a first circuit connected to the pair of data buses for connecting the pair of data buses to a common node responsive to the reset clock signal, and a second circuit connected between the common node and a ground voltage for shifting a potential at the common node to a voltage which is the predetermined voltage greater than the ground voltage.

    摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括以矩阵布置的多个存储单元，读出放大器，可操作地连接到存储单元阵列，放大从一个存储单元读出的信号，并具有一对输出 用于输出互补信号的端子，用于传送互补信号的一对数据总线，用于响应于读取操作将一对输出端连接到该对数据总线的传输门，连接到该对数据的数据输出缓冲器 用于输出输出信号的总线;以及复位电路，用于响应于复位时钟信号在每次读取操作之前将该对数据总线复位到预定电压。 复位电路包括连接到该对数据总线的第一电路，用于响应于复位时钟信号将一对数据总线连接到公共节点，以及连接在公共节点和接地电压之间的第二电路， 该公共节点为大于接地电压的预定电压的电压。

    Engine
    23.
    发明授权
    Engine 有权
    发动机

    公开(公告)号：US08857176B2

    公开(公告)日：2014-10-14

    申请号：US13123126

    申请日：2009-09-17

    申请人： Takeshi Takahashi ,  Hidenori Nomura ,  Kazuki Maetani ,  Terumitsu Takahata ,  Takao Kawabe ,  Kazuhiro Takenaka

    发明人： Takeshi Takahashi ,  Hidenori Nomura ,  Kazuki Maetani ,  Terumitsu Takahata ,  Takao Kawabe ,  Kazuhiro Takenaka

    IPC分类号： F02B37/12 ,  F02B37/00 ,  F02D41/00 ,  F02B37/22 ,  F02B37/007 ,  F02B37/24 ,  F02B37/18 ,  F02D23/00

    CPC分类号： F02D23/00 ,  F02B37/001 ,  F02B37/007 ,  F02B37/18 ,  F02B37/22 ,  F02B37/24 ,  F02B2037/122 ,  F02D41/0007 ,  F02D2200/0406 ,  Y02T10/144

    摘要： An engine provided with a variable parallel supercharging system (9) comprising a first supercharger (10) which is driven by exhaust gas which flows in a first exhaust gas route (41) and which pressurizes intake air which flows in a first intake air route (3) and also comprising a second supercharger (20) which is driven by exhaust gas which flows in a second exhaust gas route (42) and which pressurizes intake air which flows in a second intake air route (4), a supercharging pressure sensor (63) for detecting the pressure of the pressurized intake air, a first supercharger rotation sensor (61) for detecting the rotational speed of the first supercharger (10), a second supercharger rotation sensor (62) for detecting the rotational speed of the second supercharger (20), a first variable actuator (14) for adjusting the capacity of the first supercharger (10), a second variable actuator (24) for adjusting the capacity of the second supercharger (20), and a control device for controlling each of the variable actuators (14, 24). The control device controls the first variable actuator (14) based on detection signals from the supercharging pressure sensor (63) and the first supercharger rotation sensor (61) and controls the second variable actuator (24) based on detection signals from the supercharging pressure sensor (63) and the second supercharger rotation sensor (62).

    摘要翻译： 一种具有可变并联增压系统（9）的发动机，包括：第一增压器（10），其由在第一排气路径（41）中流动的排气驱动，并且对在第一进气路径中流动的进气加压 3），并且还包括由在第二排气路径（42）中流动并且在第二进气路径（4）中流动的进气加压的排气驱动的第二增压器（20），增压压力传感器 63），用于检测加压吸入空气的压力的第一增压器旋转传感器（61），用于检测第一增压器（10）的转速的第一增压器旋转传感器（61），用于检测第二增压器 （20），用于调节第一增压器（10）的容量的第一可变致动器（14），用于调节第二增压器（20）的容量的第二可变致动器（24），以及用于控制第二增压器 ch的可变致动器（14,24）。 控制装置基于来自增压压力传感器（63）和第一增压器旋转传感器（61）的检测信号来控制第一可变致动器（14），并且基于来自增压压力传感器的检测信号来控制第二可变致动器（24） （63）和第二增压器旋转传感器（62）。

    Semiconductor memory device
    26.
    发明授权
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US5619465A

    公开(公告)日：1997-04-08

    申请号：US584471

    申请日：1996-01-11

    申请人： Hidenori Nomura ,  Kenji Nagai ,  Masami Nakashima ,  Hiroshi Yamamoto ,  Isaya Sobue

    发明人： Hidenori Nomura ,  Kenji Nagai ,  Masami Nakashima ,  Hiroshi Yamamoto ,  Isaya Sobue

    IPC分类号： G11C7/06 ,  G11C11/406 ,  G11C11/4091 ,  G11C7/02

    CPC分类号： G11C11/406 ,  G11C11/4091 ,  G11C7/065

    摘要： A semiconductor memory device is disclosed, which is supplied with power from a power supply and which includes memory cells and a sense amplifier connected to the cells via bit lines. The memory device further includes a circuit for enabling the sense amplifier in response to a supplied enable signal, and for allowing the sense amplifier to rewrite cell data, read on the bit lines, into the memory cell again in self-refresh mode. The enabling circuit incorporates a noise suppression circuit which suppresses rapid changes in an operation current flowing between the power supply and the sense amplifier in order to minimize power supply related noise.

    摘要翻译： 公开了一种半导体存储器件，其从电源提供电力，并且包括存储器单元和经由位线连接到单元的读出放大器。 存储器件还包括一个电路，用于响应所提供的使能信号使读出放大器能够使能，并且允许读出放大器在自刷新模式下再次将位线上的单元数据重新读入存储器单元。 使能电路包括噪声抑制电路，其抑制在电源和读出放大器之间流动的工作电流的快速变化，以便最小化与电源相关的噪声。

    Semiconductor memory device having a plurality of selectively activated data bus limiters
    28.
    发明授权
    Semiconductor memory device having a plurality of selectively activated data bus limiters 失效
    具有多项活动数据总线限制的半导体存储器件

    公开(公告)号：US5239508A

    公开(公告)日：1993-08-24

    申请号：US730723

    申请日：1991-07-16

    申请人： Hidenori Nomura ,  Yoshiharu Kato ,  Eisaku Itoh

    发明人： Hidenori Nomura ,  Yoshiharu Kato ,  Eisaku Itoh

    IPC分类号： G11C11/409 ,  G11C7/10 ,  H03F1/30

    CPC分类号： G11C7/1069 ,  G11C7/1048 ,  G11C7/1051

    摘要： A semiconductor memory device comprises a memory cell array including a plurality of memory cells, a plurality of word lines and bit lines connected to the memory cells, a data bus for carrying data to be written in and/or read out from a selected memory cell, an addressing circuit for selecting one of the word lines and bit lines, an input buffer for outputting the electric signal indicative of the data to be written on the data bus, a current-mirror amplifier connected to the data bus for amplifying the electric signals that are read out from the memory cell on the data bus, and a limiter circuit connected to the data bus for limiting a voltage swing of the electric signals on the data bus. The limiter circuit maintains the data bus at a predetermined voltage level and limits the voltage level of the electric signals supplied to the current-mirror amplifier, wherein the limiter circuit changes the predetermined voltage level in response to a voltage level of a supply voltage that powers the current-mirror amplifier.