公开(公告)号：US08975139B2

公开(公告)日：2015-03-10

申请号：US14000901

申请日：2012-09-04

申请人： Shinichiro Miyahara ,  Toshimasa Yamamoto ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

发明人： Shinichiro Miyahara ,  Toshimasa Yamamoto ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/34 ,  H01L29/423 ,  H01L29/16

CPC分类号： H01L29/66666 ,  H01L21/3065 ,  H01L29/1608 ,  H01L29/34 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7813

摘要： A manufacturing method of a silicon carbide semiconductor device includes: forming a drift layer on a silicon carbide substrate; forming a base layer on or in a surface portion of the drift layer; forming a source region in a surface portion of the base layer; forming a trench to penetrate the base layer and to reach the drift layer; forming a gate electrode on a gate insulation film in the trench; forming a source electrode electrically connected to the source region and the base layer; and forming a drain electrode on a back surface of the substrate. The forming of the trench includes: flattening a substrate surface; and etching to form the trench after flattening.

摘要翻译： 碳化硅半导体器件的制造方法包括：在碳化硅衬底上形成漂移层; 在漂移层的表面部分上或其中形成基底层; 在所述基底层的表面部分中形成源区; 形成沟槽以穿透基层并到达漂移层; 在沟槽中的栅极绝缘膜上形成栅电极; 形成与源极区域和基极层电连接的源电极; 以及在所述基板的背面上形成漏电极。 沟槽的形成包括：使基底表面变平; 并进行蚀刻以在平坦化之后形成沟槽。

公开(公告)号：US08618555B2

公开(公告)日：2013-12-31

申请号：US13117575

申请日：2011-05-27

申请人： Naohiro Suzuki ,  Hideo Matsuki ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Jun Morimoto ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

发明人： Naohiro Suzuki ,  Hideo Matsuki ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Jun Morimoto ,  Tsuyoshi Ishikawa ,  Narumasa Soejima ,  Yukihiko Watanabe

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

摘要： The silicon carbide semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate insulating layer, a gate electrode, a source electrode, a drain electrode, and a deep layer. The deep layer is disposed under the base region and is located to a depth deeper than the trench. The deep layer is divided into a plurality of portions in a direction that crosses a longitudinal direction of the trench. The portions include a group of portions disposed at positions corresponding to the trench and arranged at equal intervals in the longitudinal direction of the trench. The group of portions surrounds corners of a bottom of the trench.

摘要翻译： 碳化硅半导体器件包括衬底，漂移层，基极区域，源极区域，沟槽，栅极绝缘层，栅极电极，源极电极，漏极电极和深层。 深层设置在基底区域下方并且位于比沟槽更深的深度。 深层在与沟槽的纵向方向交叉的方向上分成多个部分。 这些部分包括设置在与沟槽相对应的位置处的一组部分，其在沟槽的纵向方向上以相等的间隔布置。 该组部分围绕沟槽的底部的角落。

公开(公告)号：US08575689B2

公开(公告)日：2013-11-05

申请号：US13330835

申请日：2011-12-20

申请人： Tomohiro Mimura ,  Shinichiro Miyahara ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Tomohiro Mimura ,  Shinichiro Miyahara ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7397

摘要： An SiC semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate oxide film, a gate electrode, a source electrode and a drain electrode. The substrate has a Si-face as a main surface. The source region has the Si-face. The trench is provided from a surface of the source region to a portion deeper than the base region and extends longitudinally in one direction and has a Si-face bottom. The trench has an inverse tapered shape, which has a smaller width at an entrance portion than at a bottom, at least at a portion that is in contact with the base region.

摘要翻译： SiC半导体器件包括衬底，漂移层，基极区域，源极区域，沟槽，栅极氧化膜，栅电极，源电极和漏电极。 基板具有作为主表面的Si面。 源区具有Si面。 沟槽从源极区域的表面提供到比基部区域更深的部分并且在一个方向上纵向延伸并且具有Si面底部。 沟槽具有倒锥形形状，至少在与基部区域接触的部分处，入口部分处的宽度比底部宽。

公开(公告)号：US08492867B2

公开(公告)日：2013-07-23

申请号：US13164246

申请日：2011-06-20

申请人： Kensaku Yamamoto ,  Naohiro Suzuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Kensaku Yamamoto ,  Naohiro Suzuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Jun Morimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L21/20

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/66068 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/8613

摘要： A semiconductor device includes a semiconductor substrate and an electric field terminal part. The semiconductor substrate includes a substrate, a drift layer disposed on a surface of the substrate, and a base layer disposed on a surface of the drift layer. The semiconductor substrate is divided into a cell region in which a semiconductor element is disposed and a peripheral region that surrounds the cell region. The base region has a bottom face located on a same plane throughout the cell region and the peripheral region and provides an electric field relaxing layer located in the peripheral region. The electric field terminal part surrounds the cell region and a portion of the electric field relaxing layer and penetrates the electric field relaxing layer from a surface of the electric field relaxing layer to the drift layer.

摘要翻译： 半导体器件包括半导体衬底和电场端子部分。 半导体衬底包括衬底，设置在衬底的表面上的漂移层和设置在漂移层的表面上的基底层。 半导体衬底被分成其中设置半导体元件的单元区域和围绕单元区域的外围区域。 基底区域具有位于整个电池区域和外围区域的同一平面上的底面，并且提供位于周边区域中的电场弛豫层。 电场端子部围绕电池区域和电场缓和层的一部分，从电场缓和层的表面向漂移层贯通电场缓和层。

公开(公告)号：US20140191248A1

公开(公告)日：2014-07-10

申请号：US14147048

申请日：2014-01-03

申请人： Hidefumi Takaya ,  Masaru Nagao ,  Narumasa Soejima

发明人： Hidefumi Takaya ,  Masaru Nagao ,  Narumasa Soejima

IPC分类号： H01L23/62 ,  H01L29/78

CPC分类号： H01L29/7827 ,  H01L27/0251 ,  H01L29/4236 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor substrate that has an element region and a peripheral region that surrounds the element region; and a gate pad that is disposed in an area that is on a surface side of the semiconductor substrate. The element region is formed with an insulated gate semiconductor element that has a gate electrode. The peripheral region is formed with a first withstand voltage retaining structure that surrounds the element region and a second withstand voltage retaining structure that is located in a position on the first withstand voltage retaining structure side from an outer edge of the element region and on the element region side from a boundary of the first withstand voltage retaining structure on the element region side. The gate pad is electrically connected to the gate electrode and is disposed in an area in which the second withstand voltage retaining structure is formed.

摘要翻译： 半导体器件包括：半导体衬底，其具有围绕元件区域的元件区域和周边区域; 以及设置在所述半导体基板的表面侧的区域中的栅极焊盘。 元件区域由具有栅电极的绝缘栅半导体元件形成。 周边区域形成有围绕元件区域的第一耐压保持结构和位于第一耐压保持结构侧的位于元件区域的外边缘上的位置的第二耐压保持结构，并且元件 区域侧从元件区域侧的第一耐压保持结构的边界。 栅极焊盘与栅电极电连接，并且设置在形成第二耐压保持结构的区域中。

公开(公告)号：US20090134456A1

公开(公告)日：2009-05-28

申请号：US11921085

申请日：2006-05-25

申请人： Masahiro Sugimoto ,  Tetsu Kachi ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

发明人： Masahiro Sugimoto ,  Tetsu Kachi ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/207 ,  H01L29/0623 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/7788 ,  H01L29/7828 ,  H01L29/7832

摘要： The present invention aims to suppress the diffusion of p-type impurities (typically magnesium), included in a semiconductor region of a III-V compound semiconductor, into an adjoining different semiconductor region. A semiconductor device 10 of the present invention comprises a first semiconductor region 28 of gallium nitride (GaN) including p-type impurities that consist of magnesium, a second semiconductor region 34 of gallium nitride, and an impurity diffusion suppression layer 32 of silicon oxide (SiO2) located between the first semiconductor region 28 and the second semiconductor region 34.

摘要翻译： 本发明旨在抑制包含在III-V族化合物半导体的半导体区域中的p型杂质（通常为镁）扩散到邻接的不同半导体区域中。 本发明的半导体器件10包括由镁构成的p型杂质，氮化镓的第二半导体区域34和氧化硅的杂质扩散抑制层32的氮化镓（GaN）的第一半导体区域28（ SiO 2），位于第一半导体区域28和第二半导体区域34之间。

公开(公告)号：US08878290B2

公开(公告)日：2014-11-04

申请号：US14046361

申请日：2013-10-04

申请人： Hidefumi Takaya ,  Narumasa Soejima

发明人： Hidefumi Takaya ,  Narumasa Soejima

IPC分类号： H01L29/78

CPC分类号： H01L29/7831 ,  H01L29/0623 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

摘要： A semiconductor substrate of a semiconductor device includes a body region of a first conductivity type, a drift region of a second conductivity type coming into contact with a lower surface of the body region, a gate electrode that is provided in a gate trench passing through the body region and extending to the drift region and faces the body region, and a gate insulator that is provided between the gate electrode and a wall surface of the gate trench. An inverted U-shaped section is formed in a lower surface of the gate insulator, and a floating region of the first conductivity type is formed in the inverted U-shaped section. The floating region protrudes under a portion that is located at a lowermost portion in the lower surface of the gate insulator.

摘要翻译： 半导体器件的半导体衬底包括第一导电类型的主体区域，与主体区域的下表面接触的第二导电类型的漂移区域，设置在通过所述主体区域的栅极沟槽中的栅电极 并且延伸到漂移区并面向身体区域，以及设置在栅极电极和栅极沟槽的壁表面之间的栅极绝缘体。 在栅极绝缘体的下表面形成倒U字状的截面，在倒U字状的截面形成有第一导电型的浮动区域。 浮动区域在位于栅极绝缘体的下表面中的最下部的部分下方突出。

公开(公告)号：US09773883B2

公开(公告)日：2017-09-26

申请号：US15114461

申请日：2014-10-06

申请人： Akitaka Soeno ,  Yuichi Takeuchi ,  Narumasa Soejima

发明人： Akitaka Soeno ,  Yuichi Takeuchi ,  Narumasa Soejima

IPC分类号： H01L29/66 ,  H01L29/16 ,  H01L29/423 ,  H01L29/78 ,  H01L29/10 ,  H01L29/739

CPC分类号： H01L29/66068 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

摘要： A method is provided for manufacturing an insulated gate type switching device. The method includes: implanting second conductivity type impurities into a surface of a semiconductor substrate so as to form a second region of a second conductivity type in the surface; forming a third region of the second conductivity type having a second conductivity type impurity density lower than the second region on the surface by epitaxial growth: and forming a trench gate electrode.

公开(公告)号：US09640655B2

公开(公告)日：2017-05-02

申请号：US14762607

申请日：2013-01-24

申请人： Shinya Nishimura ,  Narumasa Soejima ,  Kensaku Yamamoto

发明人： Shinya Nishimura ,  Narumasa Soejima ,  Kensaku Yamamoto

IPC分类号： H01L29/78 ,  H01L29/10 ,  H01L21/311 ,  H01L21/306 ,  H01L21/225 ,  H01L21/31 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L21/265 ,  H01L21/28

CPC分类号： H01L29/7834 ,  H01L21/225 ,  H01L21/2652 ,  H01L21/28238 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7813 ,  H01L29/7841

摘要： A semiconductor device is provided with: a first conductivity type contact region; a second conductivity type body region; a first conductivity type drift region of; a trench formed through the contact region and body region from a front surface of the semiconductor substrate, wherein a bottom of the trench is positioned in the drift region; an insulating film covering an inner surface of the trench; a gate electrode accommodated in the trench in a state covered with the insulating film; and a second conductivity type floating region formed at a position deeper than the bottom of the trench, and adjacent to the bottom of the trench. The floating region includes a first layer adjacent to the bottom of the trench and a second layer formed at a position deeper than the first layer, wherein a width of the first layer is broader than a width of the second layer.

公开(公告)号：US07777252B2

公开(公告)日：2010-08-17

申请号：US11632665

申请日：2005-06-22

申请人： Masahiro Sugimoto ,  Tetsu Kachi ,  Yoshitaka Nakano ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

发明人： Masahiro Sugimoto ,  Tetsu Kachi ,  Yoshitaka Nakano ,  Tsutomu Uesugi ,  Hiroyuki Ueda ,  Narumasa Soejima

IPC分类号： H01L29/739 ,  H01L31/072

CPC分类号： H01L29/778 ,  H01L21/28 ,  H01L29/2003 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/7787

摘要： A semiconductor device has a stacked structure in which a p-GaN layer, an SI-GaN layer, and an AlGaN layer are stacked, and has a gate electrode that is formed at a top surface side of the AlGaN layer. A band gap of the AlGaN layer is wider than a band gap of the p-GaN layer and the SI-GaN layer. Moreover, impurity concentration of the SI-GaN layer is less than 1×1017 cm−3. Semiconductor devices including III-V semiconductors may have a stable normally-off operation.

摘要翻译： 半导体器件具有其中堆叠p-GaN层，SI-GaN层和AlGaN层的堆叠结构，并且具有形成在AlGaN层的顶表面侧的栅电极。 AlGaN层的带隙比p-GaN层和SI-GaN层的带隙宽。 此外，SI-GaN层的杂质浓度小于1×1017cm-3。 包括III-V半导体的半导体器件可以具有稳定的常关断操作。