公开(公告)号：US08575689B2

公开(公告)日：2013-11-05

申请号：US13330835

申请日：2011-12-20

申请人： Tomohiro Mimura ,  Shinichiro Miyahara ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Tomohiro Mimura ,  Shinichiro Miyahara ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/7397

摘要： An SiC semiconductor device includes a substrate, a drift layer, a base region, a source region, a trench, a gate oxide film, a gate electrode, a source electrode and a drain electrode. The substrate has a Si-face as a main surface. The source region has the Si-face. The trench is provided from a surface of the source region to a portion deeper than the base region and extends longitudinally in one direction and has a Si-face bottom. The trench has an inverse tapered shape, which has a smaller width at an entrance portion than at a bottom, at least at a portion that is in contact with the base region.

摘要翻译： SiC半导体器件包括衬底，漂移层，基极区域，源极区域，沟槽，栅极氧化膜，栅电极，源电极和漏电极。 基板具有作为主表面的Si面。 源区具有Si面。 沟槽从源极区域的表面提供到比基部区域更深的部分并且在一个方向上纵向延伸并且具有Si面底部。 沟槽具有倒锥形形状，至少在与基部区域接触的部分处，入口部分处的宽度比底部宽。

公开(公告)号：US09136372B2

公开(公告)日：2015-09-15

申请号：US13531793

申请日：2012-06-25

申请人： Shinichiro Miyahara ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

发明人： Shinichiro Miyahara ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/04 ,  H01L29/08 ,  H01L29/10 ,  H01L29/16

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7825 ,  H01L29/7827

摘要： In a silicon carbide semiconductor device, a plurality of trenches has a longitudinal direction in one direction and is arranged in a stripe pattern. Each of the trenches has first and second sidewalls extending in the longitudinal direction. The first sidewall is at a first acute angle to one of a (11-20) plane and a (1-100) plane, the second sidewall is at a second acute angle to the one of the (11-20) plane and the (1-100) plane, and the first acute angle is smaller than the second acute angle. A first conductivity type region is in contact with only the first sidewall in the first and second sidewalls of each of the trenches, and a current path is formed on only the first sidewall in the first and second sidewalls.

摘要翻译： 在碳化硅半导体器件中，多个沟槽在一个方向上具有纵向方向并且被布置成条纹图案。 每个沟槽具有在纵向方向上延伸的第一和第二侧壁。 第一侧壁与（11-20）面和（1-100）面中的一个成锐角，第二侧壁与（11-20）面和 （1-100）平面，第一锐角小于第二锐角。 第一导电类型区域仅与每个沟槽的第一和第二侧壁中的第一侧壁接触，并且仅在第一和第二侧壁中的第一侧壁上形成电流路径。

公开(公告)号：US20130001592A1

公开(公告)日：2013-01-03

申请号：US13531793

申请日：2012-06-25

申请人： Shinichiro Miyahara ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

发明人： Shinichiro Miyahara ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/161

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7825 ,  H01L29/7827

摘要： In a silicon carbide semiconductor device, a plurality of trenches has a longitudinal direction in one direction and is arranged in a stripe pattern. Each of the trenches has first and second sidewalls extending in the longitudinal direction. The first sidewall is at a first acute angle to one of a (11-20) plane and a (1-100) plane, the second sidewall is at a second acute angle to the one of the (11-20) plane and the (1-100) plane, and the first acute angle is smaller than the second acute angle. A first conductivity type region is in contact with only the first sidewall in the first and second sidewalls of each of the trenches, and a current path is formed on only the first sidewall in the first and second sidewalls.

摘要翻译： 在碳化硅半导体器件中，多个沟槽在一个方向上具有纵向方向并且被布置成条纹图案。 每个沟槽具有在纵向方向上延伸的第一和第二侧壁。 第一侧壁与（11-20）面和（1-100）面中的一个成锐角，第二侧壁与（11-20）面和 （1-100）平面，第一锐角小于第二锐角。 第一导电类型区域仅与每个沟槽的第一和第二侧壁中的第一侧壁接触，并且仅在第一和第二侧壁中的第一侧壁上形成电流通路。

公开(公告)号：US08525223B2

公开(公告)日：2013-09-03

申请号：US13450639

申请日：2012-04-19

申请人： Hiroki Watanabe ,  Shinichiro Miyahara ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

发明人： Hiroki Watanabe ,  Shinichiro Miyahara ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

IPC分类号： H01L21/02

CPC分类号： H01L29/7813 ,  H01L29/045 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7397

摘要： A SiC semiconductor device includes: a SiC substrate including a first or second conductive type layer and a first conductive type drift layer and including a principal surface having an offset direction; a trench disposed on the drift layer and having a longitudinal direction; and a gate electrode disposed in the trench via a gate insulation film. A sidewall of the trench provides a channel formation surface. The vertical semiconductor device flows current along with the channel formation surface of the trench according to a gate voltage applied to the gate electrode. The offset direction of the SiC substrate is perpendicular to the longitudinal direction of the trench.

摘要翻译： SiC半导体器件包括：SiC衬底，包括第一或第二导电类型层和第一导电类型漂移层，并且包括具有偏移方向的主表面; 设置在所述漂移层上并具有纵向方向的沟槽; 以及通过栅极绝缘膜设置在沟槽中的栅电极。 沟槽的侧壁提供通道形成表面。 垂直半导体器件根据施加到栅电极的栅极电压与沟道形成表面一起流动电流。 SiC衬底的偏移方向垂直于沟槽的纵向方向。

公开(公告)号：US20130330896A1

公开(公告)日：2013-12-12

申请号：US14000901

申请日：2012-09-04

申请人： Shinichiro Miyahara ,  Toshimasa Yamamoto ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

发明人： Shinichiro Miyahara ,  Toshimasa Yamamoto ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/66

CPC分类号： H01L29/66666 ,  H01L21/3065 ,  H01L29/1608 ,  H01L29/34 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7813

摘要： A manufacturing method of a silicon carbide semiconductor device includes: forming a drift layer on a silicon carbide substrate; forming a base layer on or in a surface portion of the drift layer; forming a source region in a surface portion of the base layer; forming a trench to penetrate the base layer and to reach the drift layer; forming a gate electrode on a gate insulation film in the trench; forming a source electrode electrically connected to the source region and the base layer; and forming a drain electrode on a back surface of the substrate. The forming of the trench includes: flattening a substrate surface; and etching to form the trench after flattening.

摘要翻译： 碳化硅半导体器件的制造方法包括：在碳化硅衬底上形成漂移层; 在漂移层的表面部分上或其中形成基底层; 在所述基底层的表面部分中形成源区; 形成沟槽以穿透基层并到达漂移层; 在沟槽中的栅极绝缘膜上形成栅电极; 形成与源极区域和基极层电连接的源电极; 以及在所述基板的背面上形成漏电极。 沟槽的形成包括：使基底表面变平; 并进行蚀刻以在平坦化之后形成沟槽。

公开(公告)号：US20120181551A1

公开(公告)日：2012-07-19

申请号：US13348781

申请日：2012-01-12

申请人： Shinichiro Miyahara ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

发明人： Shinichiro Miyahara ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

IPC分类号： H01L29/24

CPC分类号： H01L21/0475 ,  H01L29/045 ,  H01L29/24 ,  H01L29/42356 ,  H01L29/66068

摘要： A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate and a trench. The silicon carbide semiconductor substrate has an offset angle with respect to a (0001) plane or a (000-1) plane and has an offset direction in a direction. The trench is provided from a surface of the silicon carbide semiconductor substrate. The trench extends in a direction whose interior angle with respect to the offset direction is 30 degrees or −30 degrees.

摘要翻译： 碳化硅半导体器件包括碳化硅半导体衬底和沟槽。 碳化硅半导体衬底相对于（0001）面或（000-1）面具有偏移角，并且在<11-20>方向上具有偏移方向。 从碳化硅半导体衬底的表面提供沟槽。 沟槽沿相对于偏移方向的内角为30度或-30度的方向延伸。

公开(公告)号：US08975139B2

公开(公告)日：2015-03-10

申请号：US14000901

申请日：2012-09-04

申请人： Shinichiro Miyahara ,  Toshimasa Yamamoto ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

发明人： Shinichiro Miyahara ,  Toshimasa Yamamoto ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

IPC分类号： H01L21/336 ,  H01L29/66 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/34 ,  H01L29/423 ,  H01L29/16

CPC分类号： H01L29/66666 ,  H01L21/3065 ,  H01L29/1608 ,  H01L29/34 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/7813

摘要： A manufacturing method of a silicon carbide semiconductor device includes: forming a drift layer on a silicon carbide substrate; forming a base layer on or in a surface portion of the drift layer; forming a source region in a surface portion of the base layer; forming a trench to penetrate the base layer and to reach the drift layer; forming a gate electrode on a gate insulation film in the trench; forming a source electrode electrically connected to the source region and the base layer; and forming a drain electrode on a back surface of the substrate. The forming of the trench includes: flattening a substrate surface; and etching to form the trench after flattening.

摘要翻译： 碳化硅半导体器件的制造方法包括：在碳化硅衬底上形成漂移层; 在漂移层的表面部分上或其中形成基底层; 在所述基底层的表面部分中形成源区; 形成沟槽以穿透基层并到达漂移层; 在沟槽中的栅极绝缘膜上形成栅电极; 形成与源极区域和基极层电连接的源电极; 以及在所述基板的背面上形成漏电极。 沟槽的形成包括：使基底表面变平; 并进行蚀刻以在平坦化之后形成沟槽。

公开(公告)号：US20140175459A1

公开(公告)日：2014-06-26

申请号：US13994855

申请日：2012-02-06

申请人： Kensaku Yamamoto ,  Masato Noborio ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Kensaku Yamamoto ,  Masato Noborio ,  Hideo Matsuki ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/7397

摘要： A SiC semiconductor device includes: a semiconductor switching element having: a substrate, a drift layer and a base region stacked in this order; a source region and a contact region in the base region; a trench extending from a surface of the source region to penetrate the base region; a gate electrode on a gate insulating film in the trench; a source electrode electrically coupled with the source region and the base region; a drain electrode on a back side of the substrate; and multiple deep layers in an upper portion of the drift layer deeper than the trench. Each deep layer has upper and lower portions. A width of the upper portion is smaller than the lower portion.

摘要翻译： SiC半导体器件包括：半导体开关元件，其具有：依次层叠的基板，漂移层和基极区域; 源极区域和基极区域中的接触区域; 从源极区域的表面延伸以穿透基部区域的沟槽; 沟槽中的栅极绝缘膜上的栅电极; 源极，与源极区域和基极区域电耦合; 位于所述基板的背面的漏电极; 以及在漂移层的上部比沟槽更深的多个深层。 每个深层具有上部和下部。 上部的宽度小于下部。

公开(公告)号：US08710586B2

公开(公告)日：2014-04-29

申请号：US13229892

申请日：2011-09-12

申请人： Toshimasa Yamamoto ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Jun Morimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

发明人： Toshimasa Yamamoto ,  Masahiro Sugimoto ,  Hidefumi Takaya ,  Jun Morimoto ,  Narumasa Soejima ,  Tsuyoshi Ishikawa ,  Yukihiko Watanabe

IPC分类号： H01L29/66 ,  H01L29/15

CPC分类号： H01L29/7813 ,  H01L29/086 ,  H01L29/1608 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66068

摘要： A SiC semiconductor device includes: a substrate, a drift layer, and a base region stacked in this order; first and second source regions and a contact layer in the base region; a trench penetrating the source and base regions; a gate electrode in the trench; an interlayer insulation film with a contact hole covering the gate electrode; a source electrode coupling with the source region and the contact layer via the contact hole; a drain electrode on the substrate; and a metal silicide film. The high concentration second source region is shallower than the low concentration first source region, and has a part covered with the interlayer insulation film, which includes a low concentration first portion near a surface and a high concentration second portion deeper than the first portion. The metal silicide film on the second part has a thickness larger than the first portion.

摘要翻译： SiC半导体器件包括：依次堆叠的衬底，漂移层和基极区域; 第一和第二源极区域和基极区域中的接触层; 穿透源区和基区的沟槽; 沟槽中的栅电极; 具有覆盖所述栅电极的接触孔的层间绝缘膜; 源极通过接触孔与源极区域和接触层耦合; 衬底上的漏电极; 和金属硅化物膜。 高浓度第二源区比低浓度第一源区浅，并且具有被层间绝缘膜覆盖的部分，其包括表面附近的低浓度第一部分和比第一部分更深的高浓度第二部分。 第二部分上的金属硅化物膜的厚度大于第一部分。

公开(公告)号：US08518809B2

公开(公告)日：2013-08-27

申请号：US13308721

申请日：2011-12-01

申请人： Hiroki Watanabe ,  Yasuo Kitou ,  Yasushi Furukawa ,  Kensaku Yamamoto ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

发明人： Hiroki Watanabe ,  Yasuo Kitou ,  Yasushi Furukawa ,  Kensaku Yamamoto ,  Hidefumi Takaya ,  Masahiro Sugimoto ,  Yukihiko Watanabe ,  Narumasa Soejima ,  Tsuyoshi Ishikawa

IPC分类号： H01L21/20

CPC分类号： H01L21/0262 ,  C30B25/186 ,  C30B29/36 ,  H01L21/02378 ,  H01L21/0243 ,  H01L21/02529 ,  H01L21/02658 ,  H01L21/046 ,  H01L21/0475 ,  H01L29/04

摘要： A manufacturing method of an SiC single crystal includes preparing an SiC substrate, implanting ions into a surface portion of the SiC substrate to form an ion implantation layer, activating the ions implanted into the surface portion of the SiC substrate by annealing, chemically etching the surface portion of the SiC substrate to form an etch pit that is caused by a threading screw dislocation included in the SiC substrate and performing an epitaxial growth of SiC to form an SiC growth layer on a surface of the SiC substrate including an inner wall of the etch pit in such a manner that portions of the SiC growth layer grown on the inner wall of the etch pit join with each other.

摘要翻译： SiC单晶的制造方法包括制备SiC衬底，将离子注入到SiC衬底的表面部分中以形成离子注入层，通过退火激活注入到SiC衬底的表面部分中的离子，化学蚀刻表面 以形成由SiC衬底中的螺纹位错引起的蚀刻坑，并且在SiC衬底的表面上进行SiC的外延生长以形成SiC生长层，所述SiC生长层包括蚀刻的内壁 以使得在蚀刻坑的内壁上生长的SiC生长层的部分彼此连接的方式形成凹坑。