公开(公告)号：US06815741B2

公开(公告)日：2004-11-09

申请号：US10624612

申请日：2003-07-23

申请人： Yoshihisa Fujisaki ,  Yukio Takano ,  Tsutomu Ishiba

发明人： Yoshihisa Fujisaki ,  Yukio Takano ,  Tsutomu Ishiba

IPC分类号： H01L2980

CPC分类号： H01L29/32 ,  C30B15/00 ,  C30B29/42 ,  H01L29/207 ,  H01L2924/0002 ,  H01L2924/00

摘要： By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a III-V single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the III-V single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the III-V single crystal can be made uniform.

公开(公告)号：US08618523B2

公开(公告)日：2013-12-31

申请号：US12302740

申请日：2006-05-31

申请人： Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

发明人： Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

IPC分类号： H01L47/00

CPC分类号： G11C13/0004 ,  G11C8/08 ,  G11C13/0028 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

摘要： On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.

摘要翻译： 在嵌入作为下电极的插头（43）的绝缘膜（41）上，由氧化钽构成的绝缘膜（51）的叠层图案，由Ge-Sb-Te制成的记录层（52） 引入铟的硫属化合物和由钨或钨合金制成的上电极膜（53），从而形成相变存储器。 通过将绝缘膜（51）插入在记录层（52）和插塞（43）之间，可以实现降低相变存储器的编程电流的效果和防止记录层（52）的剥离的效果。 此外，通过使用引入了铟的Ge-Sb-Te类硫族化物作为记录层（52），绝缘膜（51）和记录层（52）之间的功函数差增大，编程 可以减小相变存储器的电压。

公开(公告)号：US08000126B2

公开(公告)日：2011-08-16

申请号：US12522744

申请日：2007-01-11

申请人： Takahiro Morikawa ,  Motoyasu Terao ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Yoshihisa Fujisaki ,  Masaharu Kinoshita ,  Yuichi Matsui

发明人： Takahiro Morikawa ,  Motoyasu Terao ,  Norikatsu Takaura ,  Kenzo Kurotsuchi ,  Nozomu Matsuzaki ,  Yoshihisa Fujisaki ,  Masaharu Kinoshita ,  Yuichi Matsui

IPC分类号： G11C11/00 ,  H01L29/66

CPC分类号： H01L45/144 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

摘要： A phase change memory is formed of a plug buried within a through-hole in an insulating film formed on a semiconductor substrate, an interface layer formed on the insulating film in which the plug is buried, a recording layer formed of a chalcogenide layer formed on the interface layer, and an upper contact electrode formed on the recording layer. The recording layer storing information according to resistance value change is made of chalcogenide material containing indium in an amount range from 20 atomic % to 38 atomic %, germanium in a range from 9 atomic % to 28 atomic %, antimony in a range from 3 atomic % to 18 atomic %, and tellurium in a range from 42 atomic % to 63 atomic %, where the content of germanium larger than or equal to the content of antimony.

摘要翻译： 相变存储器由形成在半导体衬底上的绝缘膜中的埋入通孔内的插塞形成，形成在绝缘膜上的界面层，其中埋入插塞，由硫化物层形成的记录层形成在 界面层和形成在记录层上的上接触电极。 根据电阻值变化存储信息的记录层由含有20原子％至38原子％的量的铟的含量为9原子％至28原子％的锗的硫属化物材料制成，3原子级的锑 ％〜18原子％，碲为42原子％〜63原子％，锗的含量大于或等于锑的含量。

公开(公告)号：US20110049454A1

公开(公告)日：2011-03-03

申请号：US12305890

申请日：2006-06-23

申请人： Motoyasu Terao ,  Yuichi Matsui ,  Tsuyoshi Koga ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Yoshihisa Fujisaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa ,  Yoshitaka Sasago ,  Junko Ushiyama ,  Akemi Hirotsune

发明人： Motoyasu Terao ,  Yuichi Matsui ,  Tsuyoshi Koga ,  Nozomu Matsuzaki ,  Norikatsu Takaura ,  Yoshihisa Fujisaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa ,  Yoshitaka Sasago ,  Junko Ushiyama ,  Akemi Hirotsune

IPC分类号： H01L45/00

CPC分类号： H01L45/1675 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144

摘要： In a phase-change memory, an interface layer is inserted between a chalcogenide material layer and a plug. The interface layer is arranged so as not to cover the entire interface of a plug-like electrode. When the plug is formed at an upper part than the chalcogenide layer, the degree of integration is increased. The interface layer is formed by carrying out sputtering using an oxide target, or, by forming a metal film by carrying out sputtering using a metal target followed by oxidizing the metal film in an oxidation atmosphere such as oxygen radical, oxygen plasma, etc.

摘要翻译： 在相变存储器中，界面层插入硫族化物材料层和插塞之间。 界面层被布置成不覆盖插塞状电极的整个界面。 当塞子形成在比硫族化物层的上部时，积分度增加。 通过使用氧化物靶进行溅射而形成界面层，或者通过使用金属靶进行溅射而形成金属膜，然后在氧自由基，氧等离子体等的氧化气氛中氧化金属膜。

公开(公告)号：US06294804B1

公开(公告)日：2001-09-25

申请号：US08943593

申请日：1997-10-03

申请人： Yoshihisa Fujisaki ,  Yukio Takano ,  Tsutomu Ishiba

发明人： Yoshihisa Fujisaki ,  Yukio Takano ,  Tsutomu Ishiba

IPC分类号： H01L2920

CPC分类号： H01L29/32 ,  C30B15/00 ,  C30B29/42 ,  H01L29/207 ,  H01L2924/0002 ,  H01L2924/00

摘要： By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements inthe wafer. The difference between the maximum value and minimum value of the lattice distortions of a GaAs single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the GaAs single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent matrial is the GaAs single crystal can be made uniform.

摘要翻译： 通过利用晶片中的晶格畸变分布与场效应晶体管的阈值电压分布之间的强相关性，晶片中晶格畸变的分布减小，从而减轻半导体的特性分布 砷化镓单晶在正常温度下的晶格畸变的最大值和最小值之间的差设定为至多4×10 -5，GaAs单晶中所含的Si原子的密度设定为 最多为1×10 16 cm -3，由此可以使母体为GaAs单晶的半导体元件的特性均匀。

公开(公告)号：US4775980A

公开(公告)日：1988-10-04

申请号：US759136

申请日：1985-07-26

申请人： Naoki Chinone ,  Shinji Tsuji ,  Yoshihisa Fujisaki ,  Yasutoshi Kashiwada ,  Motohisa Hirao ,  Hitoshi Nakamura ,  Akio Oishi ,  Kenji Hiruma ,  Tadashi Fukuzawa ,  Hiroyoshi Matumura

发明人： Naoki Chinone ,  Shinji Tsuji ,  Yoshihisa Fujisaki ,  Yasutoshi Kashiwada ,  Motohisa Hirao ,  Hitoshi Nakamura ,  Akio Oishi ,  Kenji Hiruma ,  Tadashi Fukuzawa ,  Hiroyoshi Matumura

IPC分类号： H01S5/10 ,  H01S5/12 ,  H01S5/183 ,  H01S3/08 ,  H01S3/19

CPC分类号： H01S5/18305 ,  H01S5/12 ,  H01S5/106 ,  H01S5/1206 ,  H01S5/1215 ,  H01S5/1225 ,  H01S5/18308 ,  H01S5/2072

摘要： A distributed feedback semiconductor laser provided with a grating which effects optical feedback by means of periodic corrugation disposed inside an optical resonator. The optical resonator has at least two regions having different Bragg wavelengths, and these regions are arranged longitudinally in the direction of an optical axis. The laser device can realize stable single longitudinal mode oscillation through variation of the refractive indexes of the regions nonuniformly around an average value.

摘要翻译： 一种配置有光栅的分布式反馈半导体激光器，其通过设置在光学谐振器内部的周期性波纹来实现光学反馈。 光谐振器具有至少两个具有不同布拉格波长的区域，并且这些区域沿光轴方向纵向布置。 激光装置可以通过使区域的折射率不均匀地围绕平均值变化来实现稳定的单纵模振荡。

公开(公告)号：US07859896B2

公开(公告)日：2010-12-28

申请号：US12162702

申请日：2006-02-02

申请人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Yoshihisa Fujisaki

发明人： Kenzo Kurotsuchi ,  Norikatsu Takaura ,  Yoshihisa Fujisaki

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0073 ,  G11C2013/0078 ,  G11C2213/79 ,  H01L27/24

摘要： A semiconductor device for high-speed reading and which has a high data-retention characteristic is provided. In a semiconductor device including a memory array having a plurality of memory cells provided at intersecting points of a plurality of word lines and a plurality of bit lines, where each memory cell includes an information memory section and a select element, information is programmed by a first pulse (reset operation) for programming information flowing in the bit line, a second pulse (set operation) different from the first pulse, and information is read by a third pulse (read operation), such that the current directions of the second pulse and the third pulse are opposite to each other.

摘要翻译： 提供了一种用于高速读取并具有高数据保持特性的半导体器件。 在包括具有设置在多个字线和多个位线的交叉点的多个存储单元的存储器阵列的半导体器件中，其中每个存储器单元包括信息存储器部分和选择元件，信息由 用于对在位线中流动的信息进行编程的第一脉冲（复位操作），与第一脉冲不同的第二脉冲（设置操作），并且通过第三脉冲（读取操作）读取信息，使得第二脉冲 并且第三脉冲彼此相反。

公开(公告)号：US07767997B2

公开(公告)日：2010-08-03

申请号：US12169818

申请日：2008-07-09

申请人： Yoshitaka Sasago ,  Motoyasu Terao ,  Norikatsu Takaura ,  Yoshihisa Fujisaki ,  Tomoyuki Kodama ,  Nobuyuki Arasawa

发明人： Yoshitaka Sasago ,  Motoyasu Terao ,  Norikatsu Takaura ,  Yoshihisa Fujisaki ,  Tomoyuki Kodama ,  Nobuyuki Arasawa

IPC分类号： H01L29/06 ,  H01L29/08

CPC分类号： H01L45/1206 ,  G06N3/063 ,  G11C13/0011 ,  H01L45/085 ,  H01L45/142 ,  H01L45/146 ,  H01L45/1675

摘要： A nonvolatile, sophisticated semiconductor device with a small surface area and a simple structure capable of switching connections between three or more electrodes. In a semiconductor device at least one of the electrodes contains atoms such as copper or silver in the solid electrolyte capable of easily moving within the solid electrolyte, and those electrodes face each other and applying a voltage switches the voltage on and off by generating or annihilating the conductive path between the electrodes. Moreover applying a voltage to a separate third electrode can annihilate the conductive path formed between two electrodes without applying a voltage to the two electrode joined by the conductive path.

摘要翻译： 具有小表面积的非易失性，复杂的半导体器件和能够切换三个或更多个电极之间的连接的简单结构。 在半导体器件中，电极中的至少一个在固体电解质中含有诸如铜或银之类的原子，能够容易地在固体电解质内移动，并且这些电极彼此面对并且施加电压通过产生或消除电压来开启和关闭电压 电极之间的导电路径。 此外，向单独的第三电极施加电压可以消除在两个电极之间形成的导电路径，而不向由导电路径连接的两个电极施加电压。

公开(公告)号：US20100012917A1

公开(公告)日：2010-01-21

申请号：US12302740

申请日：2006-05-31

申请人： Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

发明人： Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

IPC分类号： H01L47/00

CPC分类号： G11C13/0004 ,  G11C8/08 ,  G11C13/0028 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

摘要： On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.

摘要翻译： 在嵌入作为下电极的插头（43）的绝缘膜（41）上，由氧化钽构成的绝缘膜（51）的叠层图案，由Ge-Sb-Te制成的记录层（52） 引入铟的硫属化合物和由钨或钨合金制成的上电极膜（53），从而形成相变存储器。 通过将绝缘膜（51）插入在记录层（52）和插塞（43）之间，可以实现降低相变存储器的编程电流的效果和防止记录层（52）的剥离的效果。 此外，通过使用引入了铟的Ge-Sb-Te类硫族化物作为记录层（52），绝缘膜（51）和记录层（52）之间的功函数差增大，编程 可以减小相变存储器的电压。

公开(公告)号：US20090039336A1

公开(公告)日：2009-02-12

申请号：US12176606

申请日：2008-07-21

申请人： Motoyasu Terao ,  Yoshitaka Sasago ,  Kenzo Kurotsuchi ,  Kazuo Ono ,  Yoshihisa Fujisaki ,  Norikatsu Takaura ,  Riichiro Takemura

发明人： Motoyasu Terao ,  Yoshitaka Sasago ,  Kenzo Kurotsuchi ,  Kazuo Ono ,  Yoshihisa Fujisaki ,  Norikatsu Takaura ,  Riichiro Takemura

IPC分类号： H01L45/00

CPC分类号： G11C11/5614 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/11 ,  G11C2213/15 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/141 ,  H01L45/142 ,  H01L45/1675

摘要： The performance of a semiconductor device capable of storing information is improved. A memory layer of a memory element is formed by a first layer at a bottom electrode side and a second layer at a top electrode side. The first layer contains 20-70 atom % of at least one element of a first element group of Cu, Ag, Au, Al, Zn, and Cd, contains 3-40 atom % of at least one element of a second element group of V, Nb, Ta, Cr, Mo, W, Ti, Zr, Hf, Fe, Co, Ni, Pt, Pd, Rh, Ir, Ru, Os, and lanthanoid elements, and contains 20-60 atom % of at least one element of a third element group of S, Se, and Te. The second layer contains 5-50 atom % of at least one element of the first element group, 10-50 atom % of at least one element of the second element group, and 30-70 atom % of oxygen.

摘要翻译： 提高了能够存储信息的半导体装置的性能。 存储元件的存储层由底部电极侧的第一层和顶部电极侧的第二层形成。 第一层含有20-70原子％的Cu，Ag，Au，Al，Zn和Cd的第一元素基团的至少一种元素，含有3-40原子％的至少一种元素的第二元素基团 V，Nb，Ta，Cr，Mo，W，Ti，Zr，Hf，Fe，Co，Ni，Pt，Pd，Rh，Ir，Ru，Os和镧系元素，至少含有20-60原子％ S，Se和Te的第三要素组的一个元素。 第二层含有5-50原子％的第一元素基团的至少一个元素，10-50原子％的第二元素基团的至少一个元素和30-70原子％的氧。