公开(公告)号：US08513938B2

公开(公告)日：2013-08-20

申请号：US13316522

申请日：2011-12-11

申请人： Suguru Tachibana ,  Hiroyuki Matsunami ,  Yukinobu Tanida

发明人： Suguru Tachibana ,  Hiroyuki Matsunami ,  Yukinobu Tanida

IPC分类号： G05F3/16 ,  G05F3/20

CPC分类号： G05F3/30

摘要： A reference voltage circuit includes a first amplifier, a first load device and a first PN junction device, second and third load devices and a second PN junction device, an offset voltage reduction circuit, a coupling node potential takeout circuit, and an area adjustment circuit. The offset voltage reduction circuit is configured to reduce an offset voltage between the first and second input terminals at the first amplifier, and the coupling node potential takeout circuit is configured to take out potentials of the first and second coupling nodes. The area adjustment circuit is configured to adjust an area of the second PN junction device in accordance with the potentials of the first and second coupling nodes which are taken out by the coupling node potential takeout circuit.

摘要翻译： 参考电压电路包括第一放大器，第一负载装置和第一PN结装置，第二和第三负载装置和第二PN结装置，偏移电压降低电路，耦合节点势能取出电路和区域调整电路 。 偏移电压降低电路被配置为减少第一放大器处的第一和第二输入端之间的偏移电压，并且耦合节点电势取出电路被配置为取出第一和第二耦合节点的电位。 区域调整电路被配置为根据由耦合节点电势取出电路取出的第一和第二耦合节点的电位来调整第二PN结装置的面积。

公开(公告)号：USRE43840E1

公开(公告)日：2012-12-04

申请号：US12926030

申请日：2010-10-21

申请人： Mitsuhiro Kataoka ,  Yuuichi Takeuchi ,  Masami Naito ,  Rajesh Kumar ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Mitsuhiro Kataoka ,  Yuuichi Takeuchi ,  Masami Naito ,  Rajesh Kumar ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L31/0312

CPC分类号： H01L29/66068 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/8083

摘要： A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is . A trench is formed on the SiC to have a stripe structure extending toward a direction. An SiC epitaxial layer is formed on an inside surface of the trench.

摘要翻译： 碳化硅（SiC）衬底设置有离轴取向{0001}表面，其离轴方向<11-20>。 在SiC上形成沟槽以具有向<11-20>方向延伸的条纹结构。 在沟槽的内表面上形成SiC外延层。

公开(公告)号：US07834673B2

公开(公告)日：2010-11-16

申请号：US12342780

申请日：2008-12-23

申请人： Hiroyuki Matsunami

发明人： Hiroyuki Matsunami

IPC分类号： H03H11/26

CPC分类号： H03K7/08 ,  H03K5/133 ,  H03K2005/00032 ,  H03K2005/00058

摘要： A variable delay circuit comprising a first delay element configured to delay an input signal, a second delay element coupled to the first delay element in parallel and also configured to delay the input signal, a control current supply section configured to supply control currents for adjusting a delay amount of the first delay element and a delay amount of the second delay element, and an output signal selecting section configured to select any one of an output signal from the first delay element and an output signal from the second delay element according to a selecting signal for selecting delay time of the input signal.

摘要翻译： 一种可变延迟电路，包括被配置为延迟输入信号的第一延迟元件，并联耦合到第一延迟元件的第二延迟元件，并且还被配置为延迟输入信号;控制电流供应部分，被配置为提供控制电流， 第一延迟元件的延迟量和第二延迟元件的延迟量，以及输出信号选择部分，被配置为根据选择从第一延迟元件输出的输出信号和来自第二延迟元件的输出信号中的任何一个 用于选择输入信号的延迟时间的信号。

公开(公告)号：US20090315082A1

公开(公告)日：2009-12-24

申请号：US12552212

申请日：2009-09-01

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/808

CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

摘要翻译： 横向结型场效应晶体管包括布置在源极/漏极区之间的第三半导体层中的第一栅电极层，具有在第二半导体层上延伸的下表面，并且掺杂有比第二半导体层更重的p型杂质 以及布置在源极/漏极区域之间的第五半导体层中的第二栅极电极层，具有在第四半导体层上延伸的下表面，具有与第一栅极电极层基本相同的p型杂质浓度，以及 具有与第一栅极电极层相同的电位。 因此，横向结型场效应晶体管具有可以在保持良好的击穿电压特性的同时降低导通电阻的结构。

公开(公告)号：US07622763B2

公开(公告)日：2009-11-24

申请号：US10565624

申请日：2004-07-28

申请人： Jun Suda ,  Hiroyuki Matsunami

发明人： Jun Suda ,  Hiroyuki Matsunami

IPC分类号： H01L29/792

CPC分类号： H01L21/28158 ,  H01L21/049 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/267 ,  H01L29/511 ,  H01L29/66068 ,  H01L29/78 ,  H01L29/7883 ,  H01L29/802 ,  H01L29/803

摘要： A field effect transistor comprises a SiC substrate 1, a source 3a and a drain 3b formed on the surface of the SiC substrate 1, an insulating structure comprising an AlN layer 5 formed in contact with the SiC surface and having a thickness of one molecule-layer or greater, and a SiO2 layer formed thereon, and a gate electrode 15 formed on the insulation structure. Leakage current can be controlled while the state of interface with SiC is maintained in a good condition.

摘要翻译： 场效应晶体管包括SiC衬底1，形成在SiC衬底1的表面上的源极3a和漏极3b，绝缘结构，其包括与SiC表面接触形成的AlN层5， 层或更大，以及形成在其上的SiO 2层，以及形成在绝缘结构上的栅电极15。 可以控制漏电流，同时与SiC的界面状态保持良好状态。

公开(公告)号：US20060202238A1

公开(公告)日：2006-09-14

申请号：US11402701

申请日：2006-04-11

申请人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Kazuhiro Fujikawa ,  Shin Harada ,  Kenichi Hirotsu ,  Satoshi Hatsukawa ,  Takashi Hoshino ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L31/112

CPC分类号： H01L29/0634 ,  H01L29/1058 ,  H01L29/1066 ,  H01L29/42316 ,  H01L29/66893 ,  H01L29/808

摘要： A lateral junction field effect transistor includes a first gate electrode layer arranged in a third semiconductor layer between source/drain region layers, having a lower surface extending on the second semiconductor layer, and doped with p-type impurities more heavily than the second semiconductor layer, and a second gate electrode layer arranged in a fifth semiconductor layer between the source/drain region layers, having a lower surface extending on a fourth semiconductor layer, having substantially the same concentration of p-type impurities as the first gate electrode layer, and having the same potential as the first gate electrode layer. Thereby, the lateral junction field effect transistor has a structure, which can reduce an on-resistance while maintaining good breakdown voltage properties.

公开(公告)号：US20060180077A1

公开(公告)日：2006-08-17

申请号：US10549683

申请日：2004-03-18

申请人： Jun Suda ,  Hiroyuki Matsunami ,  Norio Onojima

发明人： Jun Suda ,  Hiroyuki Matsunami ,  Norio Onojima

IPC分类号： C30B23/00 ,  C30B25/00 ,  C30B28/12 ,  C30B28/14

CPC分类号： C30B29/406 ,  C30B23/002 ,  C30B29/403 ,  H01L21/02378 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02631 ,  H01L21/02658 ,  H01L21/02661

摘要： SiC is a very stable substance, and it is difficult to control the condition of a SiC surface to be suitable for crystal growth in conventional Group III nitride crystal growing apparatuses. This problem is solved as follows. The surface of a SiC substrate 1 is rendered into a step-terrace structure by performing a heating process in an atmosphere of HCl gas. The surface of the SiC substrate 1 is then treated sequentially with aqua regia, hydrochloric acid, and hydrofluoric acid. A small amount of silicon oxide film formed on the surface of the SiC substrate 1 is etched so as to form a clean SiC surface 3 on the substrate surface. The SiC substrate 1 is then installed in a high-vacuum apparatus and the pressure inside is maintained at ultrahigh vacuum (such as 10−6 to 10−8 Pa). In the ultrahigh vacuum state, a process of irradiating the surface with a Ga atomic beam 5 at time t1 at temperature of 800° C. or lower and performing a heating treatment at 800° C. or higher is repeated at least once. The temperature is then set to the growth temperature of an AlN film, and the SiC substrate surface 3 is initially irradiated with —Al atoms 8a in ultrahigh vacuum state, followed by the feeding of N atoms 8b.

摘要翻译： SiC是非常稳定的物质，在传统的III族氮化物晶体生长装置中难以控制SiC表面适合于晶体生长的状态。 这个问题解决如下。 通过在HCl气体气氛中进行加热处理，将SiC衬底1的表面制成台阶平台结构。 然后依次用王水，盐酸和氢氟酸处理SiC衬底1的表面。 蚀刻形成在SiC衬底1的表面上的少量氧化硅膜，从而在衬底表面上形成清洁的SiC表面3。 然后将SiC基板1安装在高真空装置中，并且内部的压力保持在超高真空（例如10 -6至10 -8 Pa）。 在超高真空状态下，在800℃以下的温度下，在时刻t 1的Ga原子束5照射表面，进行800℃以上的加热处理，至少重复一次。 然后将温度设定为AlN膜的生长温度，并且首先用超高真空状态的-Al原子8a照射SiC衬底表面3，然后馈送N原子8b。

公开(公告)号：US20050057241A1

公开(公告)日：2005-03-17

申请号：US10792810

申请日：2004-03-05

申请人： Yasukazu Ono ,  Koji Okada ,  Hiroyuki Matsunami

发明人： Yasukazu Ono ,  Koji Okada ,  Hiroyuki Matsunami

IPC分类号： G01R23/165 ,  G01R19/00 ,  G01R23/00 ,  G01R31/28

CPC分类号： G01R31/2824 ,  G01R19/0007

摘要： An object of this invention is to provide a band distribution inspecting device and band distribution inspecting method capable of carrying out inspection on whether or not a scattered oscillation signal oscillated containing a frequency variation from the fundamental frequency with the fundamental frequency as a reference point has a band distribution rapidly, with a simple way and at a cheap price. A scattered oscillation signal SSS inputted to a band distribution detecting section 22 is outputted as a predetermined band pass signal SBP through a band pass filter 17 having a predetermined pass band of a predetermined narrow-band width Δf within a band distribution. This signal is converted to a root-mean-square value by a smoother 19, smoothed by a capacitor C1 and transferred to a general purpose inspecting device 21 as a DC signal SAV. The DC signal SAV is compared with a predetermined voltage value VX by a comparator 25 and its comparison result is judged by a judging section 25 and then, an inspection result is outputted as a judging signal J. As a result, an edge frequency in the band distribution of the scattered oscillation signal SSS and disturbance of frequency variation within/out of the band and dullness in waveform and the like can be inspected for.

摘要翻译： 本发明的目的是提供一种能够对以基频为基准的包含来自基频的频率变化的振荡信号是否具有振荡的频带分布检查装置和频带分布检查方法进行检查 乐队分布迅速，以简单的方式和便宜的价格。 输入到频带分布检测部分22的散射振荡信号SSS作为预定的带通信号SBP通过具有预定窄带宽度Deltaf的预定通带的带通滤波器17输出。 该信号由平滑器19转换成均方根值，由电容器C1平滑，并作为DC信号SAV传送到通用检测装置21。 通过比较器25将DC信号SAV与预定的电压值VX进行比较，并且判断部25判断其比较结果，然后作为判断信号J输出检查结果。结果，边缘频率 可以检查散射振荡信号SSS的频带分布和波段内/频带内的频率变化的干扰以及波形等中的钝度。

公开(公告)号：US06853006B2

公开(公告)日：2005-02-08

申请号：US10630978

申请日：2003-07-31

申请人： Mitsuhiro Kataoka ,  Yuuichi Takeuchi ,  Masami Naito ,  Rajesh Kumar ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

发明人： Mitsuhiro Kataoka ,  Yuuichi Takeuchi ,  Masami Naito ,  Rajesh Kumar ,  Hiroyuki Matsunami ,  Tsunenobu Kimoto

IPC分类号： H01L29/80 ,  H01L21/04 ,  H01L21/337 ,  H01L29/04 ,  H01L29/24 ,  H01L29/808 ,  H01L31/312

CPC分类号： H01L29/66068 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/8083

摘要： A silicon carbide (SiC) substrate is provided with an off-oriented {0001} surface whose off-axis direction is . A trench is formed on the SiC to have a stripe structure extending toward a direction. An SiC epitaxial layer is formed on an inside surface of the trench.

摘要翻译： 碳化硅（SiC）衬底设置有离轴取向{0001}表面，其离轴方向<11-20>。 在SiC上形成沟槽以具有向<11-20>方向延伸的条纹结构。 在沟槽的内表面上形成SiC外延层。

公开(公告)号：US06577260B2

公开(公告)日：2003-06-10

申请号：US09819719

申请日：2001-03-29

申请人： Koji Okada ,  Hiroyuki Matsunami

发明人： Koji Okada ,  Hiroyuki Matsunami

IPC分类号： H03M166

CPC分类号： H03K17/04106 ,  H03K17/162 ,  H03K17/693 ,  H03M1/745

摘要： A Digital/Analog converter comprising a plurality of current sources, and a selecting circuit for selecting a current source from the plurality of current sources on the basis of a digital signal. The selecting circuit includes a first transistor in which the digital signal is supplied. The selecting circuit also includes a second transistor with the same conductivity type as the first transistor for receiving an inverted digital signal of the digital signal. The second transistor is connected to the output of the first transistor.

摘要翻译： 一种数字/模拟转换器，包括多个电流源，以及选择电路，用于根据数字信号从多个电流源中选择电流源。 选择电路包括其中提供数字信号的第一晶体管。 选择电路还包括具有与第一晶体管相同的导电类型的第二晶体管，用于接收数字信号的反相数字信号。 第二晶体管连接到第一晶体管的输出。