公开(公告)号：US5909052A

公开(公告)日：1999-06-01

申请号：US449722

申请日：1995-05-24

申请人： Hiroyuki Ohta ,  Hideo Miura ,  Mitsuo Usami ,  Masatsugu Kametani ,  Munetoshi Zen ,  Noriaki Okamoto

发明人： Hiroyuki Ohta ,  Hideo Miura ,  Mitsuo Usami ,  Masatsugu Kametani ,  Munetoshi Zen ,  Noriaki Okamoto

IPC分类号： G06F9/38 ,  G06F15/167 ,  H01L21/98 ,  H01L25/065 ,  H01L29/06 ,  H01L29/04

CPC分类号： G06F9/3879 ,  G06F15/167 ,  G06F9/3877 ,  H01L24/24 ,  H01L24/82 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/50 ,  H01L2223/54426 ,  H01L2224/24137 ,  H01L2224/24225 ,  H01L2224/24227 ,  H01L2224/95136 ,  H01L29/0657 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04953 ,  H01L2924/10157 ,  H01L2924/10158 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/351

摘要： Prevention of reduction in the production yield due to the increase in the area of a semiconductor chip permits a sophisticated-performance single-chip semiconductor device to be fabricated. This also permits a many-kind small-amount production of semiconductor devices to be implemented. After plural semiconductor chips 2 and 3 are fabricated separately, only defect-free chips of them are selected. The selected defect-free chips are connected in contact between their side walls of their densest faces of atoms of their substrates so that the surfaces 4a and 4b where elements are to be formed are located in the same plane. Thus, even when the chip area is increased, reduction of the production yield can be prevented, thereby permitting a large-area sophisticated-performance single chip semiconductor device to be fabricated. If many kinds of semiconductor chips are prepared and connected in their combination in a variety of forms, it is possible to realize a many-kind small-amount production of semiconductor devices.

摘要翻译： 由于半导体芯片面积的增加，防止生产成品率的下降，可以制造精密性能的单芯片半导体器件。 这也允许实现多种少量的半导体器件的生产。 在单独制造多个半导体芯片2和3之后，仅选择它们的无缺陷芯片。 所选择的无缺陷芯片在它们的基板的最密实面的侧壁之间接触连接，使得要形成元件的表面4a和4b位于同一平面中。 因此，即使在芯片面积增加的情况下，也可以防止生产成品率的降低，从而可以制造大面积复杂性能的单芯片半导体器件。 如果准备多种半导体芯片并以各种形式组合连接，则可以实现多种少量的半导体器件的制造。

公开(公告)号：US07205617B2

公开(公告)日：2007-04-17

申请号：US10330196

申请日：2002-12-30

申请人： Hiroyuki Ohta ,  Yukihiro Kumagai ,  Yasuo Sonobe ,  Kousuke Ishibashi ,  Yasushi Tainaka ,  Masafumi Miyamoto ,  Hideo Miura

发明人： Hiroyuki Ohta ,  Yukihiro Kumagai ,  Yasuo Sonobe ,  Kousuke Ishibashi ,  Yasushi Tainaka ,  Masafumi Miyamoto ,  Hideo Miura

IPC分类号： H01L29/76 ,  H01L29/00

CPC分类号： B82Y10/00 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/66439 ,  H01L29/7846

摘要： A semiconductor device has p-channel field effect transistors disposed in a lattice shape. In order to generate compression stress in the channel of a p-channel field effect transistor, a long active region of a plurality of transistors is divided for each gate electrode and a sufficiently thin shallow trench isolation (STI) is formed between adjacent gate electrodes. The drain current characteristics can be improved.

摘要翻译： 半导体器件具有以栅格形状设置的p沟道场效应晶体管。 为了在p沟道场效应晶体管的沟道中产生压缩应力，对于每个栅电极划分多个晶体管的长有源区，并且在相邻栅电极之间形成足够薄的浅沟槽隔离（STI）。 可以提高漏极电流特性。

公开(公告)号：US20060252186A1

公开(公告)日：2006-11-09

申请号：US11480912

申请日：2006-07-06

申请人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

发明人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

IPC分类号： H01L21/84

CPC分类号： H01L21/28097 ,  H01L21/28035 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/32053 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/823437 ,  H01L23/485 ,  H01L23/53257 ,  H01L23/53271 ,  H01L28/40 ,  H01L29/4925 ,  H01L29/4975 ,  H01L2924/0002 ,  Y10T117/10 ,  Y10T117/1004 ,  H01L2924/00

摘要： In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.

摘要翻译： 在半导体衬底4上的氧化硅膜5上通过氧化硅膜5形成电极2时，例如，栅电极2被构成为多个多晶硅层6的叠层结构。 栅电极2的部分通过制造具有沉积非晶层的工艺的薄膜的方法和使该非晶材料结晶（再结晶）的方法形成。 在这种情况下，非晶层的沉积被分开多次进行，使得一次沉积的非晶层的厚度不大于根据根据下式确定的临界应力值规定的厚度 在每个非晶层的沉积过程完成之后，非晶材料结晶，重复沉积非晶层的过程和结晶非晶材料的过程，由此多晶层6的层压结构具有必要的 获得膜厚度。 利用上述结构，可以防止半导体器件的电特性的恶化和层之间的剥离等缺陷的发生，层中的裂纹等，并且可以获得 通过多晶材料的层叠，具有所需膜厚度的小晶粒尺寸的多晶层。

公开(公告)号：US07084477B2

公开(公告)日：2006-08-01

申请号：US10600771

申请日：2003-06-23

申请人： Norio Ishitsuka ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Masahito Takahashi ,  Norio Suzuki ,  Shuji Ikeda ,  Hideki Tanaka ,  Hiroyuki Mima

发明人： Norio Ishitsuka ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Masahito Takahashi ,  Norio Suzuki ,  Shuji Ikeda ,  Hideki Tanaka ,  Hiroyuki Mima

IPC分类号： H01L29/00

CPC分类号： H01L27/11526 ,  H01L21/28123 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/105 ,  H01L27/11546

摘要： To suppress defects occurred in a semiconductor substrate, a semiconductor device is constituted by having: the semiconductor substrate; an element isolating region having a trench formed in the semiconductor substrate and an embedding insulating film which is embedded into the trench; an active region formed adjacent to the element isolating region, in which a gate insulating film is formed and a gate electrode is formed on the gate insulating film; and a region formed in such a manner that at least a portion of the gate electrode is positioned on the element isolating region, and a first edge surface of an upper side of the embedding insulating film in a first element isolating region where the gate electrode is positioned is located above a second edge surface of the embedding insulating film in a second element isolating region where the gate electrode film is not positioned.

摘要翻译： 为了抑制在半导体衬底中发生的缺陷，半导体器件通过具有：半导体衬底; 具有形成在所述半导体衬底中的沟槽的元件隔离区域和嵌入所述沟槽中的嵌入绝缘膜; 形成在元件隔离区域附近形成的有源区，其中形成栅极绝缘膜并在栅极绝缘膜上形成栅电极; 以及形成为使得栅电极的至少一部分位于元件隔离区域上的区域，以及在栅电极为第一元件隔离区域的嵌入绝缘膜的上侧的第一边缘表面 定位在位于绝缘膜的第二边缘表面上方的第二元件隔离区域中，栅极电极膜未被定位。

公开(公告)号：US07064437B2

公开(公告)日：2006-06-20

申请号：US10184932

申请日：2002-07-01

申请人： Tomio Iwasaki ,  Hideo Miura ,  Takashi Nakajima ,  Hiroyuki Ohta ,  Shinji Nishihara ,  Masashi Sahara

发明人： Tomio Iwasaki ,  Hideo Miura ,  Takashi Nakajima ,  Hiroyuki Ohta ,  Shinji Nishihara ,  Masashi Sahara

IPC分类号： H01L23/48 ,  H01L29/94

CPC分类号： H01L21/76844 ,  H01L21/32051 ,  H01L21/76843 ,  H01L21/7685 ,  H01L23/53219 ,  H01L23/53223 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device having high reliability, high yield, and such a interconnection structure as short hardly occurs. The semiconductor device comprises a semiconductor substrate, metal conductors formed on a side of a main face of the substrate which metal conductors contain aluminum as main constituent thereof and copper as an additive element, the metal conductors being made to contain such an element as to suppress the precipitation of copper or being made to have such a film adjacent to the metal conductor as to suppress the precipitation of copper.

公开(公告)号：US06943076B2

公开(公告)日：2005-09-13

申请号：US09943843

申请日：2001-08-30

申请人： Tomio Iwasaki ,  Hideo Miura ,  Hiroyuki Ohta ,  Hiroshi Moriya

发明人： Tomio Iwasaki ,  Hideo Miura ,  Hiroyuki Ohta ,  Hiroshi Moriya

IPC分类号： H01L29/43 ,  H01L21/28 ,  H01L21/316 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78 ,  H01L21/336

CPC分类号： H01L29/517 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31604 ,  H01L27/10814 ,  H01L27/10873 ,  H01L27/10882 ,  H01L29/4966 ,  H01L29/513

摘要： Gate insulation films each containing titanium oxide as a primary constituent material are formed on one major surface of a semiconductor substrate. Gate electrode films are formed in contact with the gate insulation films. The gate electrode films contain ruthenium oxide or alternatively iridium oxide as a primary constituent material. In order to prevent electrically conductive elements from diffusing into titanium oxide of the gate insulation films, ruthenium oxide or iridium oxide is effectively used as a primary constituent material of the gate electrodes. A semiconductor device can be realized in which occurrence of a leak current is suppressed by increasing a physical film thickness while sustaining desired dielectric characteristic.

摘要翻译： 在半导体衬底的一个主表面上形成各自含有氧化钛作为主要构成材料的栅极绝缘膜。 形成与栅极绝缘膜接触的栅极电极膜。 栅极电极膜含有氧化钌或氧化铱作为主要构成材料。 为了防止导电元件扩散到栅极绝缘膜的氧化钛中，氧化钌或氧化铱被有效地用作栅电极的主要构成材料。 可以实现半导体器件，其中通过在保持期望的介电特性的同时增加物理膜厚度来抑制泄漏电流的发生。

公开(公告)号：US06686274B1

公开(公告)日：2004-02-03

申请号：US09787743

申请日：2001-06-08

申请人： Hiromi Shimazu ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Shuji Ikeda

发明人： Hiromi Shimazu ,  Tomio Iwasaki ,  Hiroyuki Ohta ,  Hideo Miura ,  Shuji Ikeda

IPC分类号： H01L2144

CPC分类号： H01L29/665 ,  H01L21/28518 ,  H01L21/76877

摘要： In a semiconductor device having a cobalt silicide film, at least nickel or iron is contained in the cobalt silicide film for preventing the rise of resistance incidental to thinning of the film.

摘要翻译： 在具有钴硅化物膜的半导体器件中，钴硅化物膜中至少含有镍或铁，以防止附着于薄膜变薄的电阻上升。

公开(公告)号：US06573112B2

公开(公告)日：2003-06-03

申请号：US10238690

申请日：2002-09-11

申请人： Ryuji Kono ,  Akihiko Ariga ,  Hideyuki Aoki ,  Hiroyuki Ohta ,  Yoshishige Endo ,  Masatoshi Kanamaru ,  Atsushi Hosogane ,  Shinji Tanaka ,  Naoto Ban ,  Hideo Miura

发明人： Ryuji Kono ,  Akihiko Ariga ,  Hideyuki Aoki ,  Hiroyuki Ohta ,  Yoshishige Endo ,  Masatoshi Kanamaru ,  Atsushi Hosogane ,  Shinji Tanaka ,  Naoto Ban ,  Hideo Miura

IPC分类号： H01L2166

CPC分类号： H01L21/6836 ,  H01L22/20 ,  H01L2221/68327 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/00

摘要： Semiconductor device chips manufacturing and inspecting method is disclosed in which a semiconductor wafer is cut into individual LSI chips. The LSI chips are rearranged and integrated into a predetermined number. The cut LSI chips are integrated in a jig having openings with a size commensurate with the dimensions of the LSI chip. At least one part of the jig having such openings has a coefficient of thermal expansion that is approximately equal to that of the LSI chips. The integrated predetermined number of chips are subjected to an inspection process in a subsequent inspection step thereby improving efficiency and reducing cost.

公开(公告)号：US06521932B1

公开(公告)日：2003-02-18

申请号：US09525029

申请日：2000-03-14

申请人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Tomio Iwasaki ,  Isamu Asano

发明人： Yukihiro Kumagai ,  Hideo Miura ,  Hiroyuki Ohta ,  Tomio Iwasaki ,  Isamu Asano

IPC分类号： H01L27108

CPC分类号： H01L21/7687 ,  H01L23/53238 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10894 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： It is an object of the present invention to provide a high-reliability semiconductor device having a storage capacitor and wiring using copper for a main conductive film. Under the above object, the present invention provides a semiconductor device comprising: a semiconductor substrate; a storage capacitor formed on the main surface side of the semiconductor substrate and being a first electrode and a second electrode arranged so as to put a capacitor insulation film; a wiring conductor formed on the main surface side of the semiconductor substrate and including the copper (Cu) element; and a first film formed on the surface of the wiring conductor; wherein a material configuring the first film and a material configuring the first electrode and/or the second electrode include the same element.

公开(公告)号：US07442593B2

公开(公告)日：2008-10-28

申请号：US11480912

申请日：2006-07-06

申请人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

发明人： Takashi Nakajima ,  Hideo Miura ,  Hiroyuki Ohta ,  Noriaki Okamoto

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L21/28097 ,  H01L21/28035 ,  H01L21/28518 ,  H01L21/28525 ,  H01L21/32053 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/823437 ,  H01L23/485 ,  H01L23/53257 ,  H01L23/53271 ,  H01L28/40 ,  H01L29/4925 ,  H01L29/4975 ,  H01L2924/0002 ,  Y10T117/10 ,  Y10T117/1004 ,  H01L2924/00

摘要： In forming an electrode 2 on a silicon oxide film 5 on a semiconductor substrate 4 through a silicon oxide film 5, for example, the gate electrode 2 is structured in a laminated structure of a plurality of polycrystalline silicon layers 6. The portion of the gate electrode 2 is formed by a method of manufacturing a thin film having a process of depositing amorphous layers and a process of crystallizing (recrystallizing) this amorphous material. In this case, depositing of the amorphous layers is carried out dividedly by a plurality of times so that the thickness of an amorphous layer to be deposited at one time is not larger than a thickness to be prescribed by a critical stress value determined according to a fail event, the amorphous material is crystallized after each process of depositing each amorphous layer has been finished, and the process of depositing amorphous layers and the process of crystallizing the amorphous material are repeated, whereby a laminated structure of the polycrystalline layer 6 having a necessary film thickness is obtained. With the above-described arrangement, it is possible to prevent a deterioration of electric characteristics of a semiconductor device and an occurrence of a defect, such as a peeling off between layers, cracks in a layer, etc., and it is possible to obtain a polycrystalline layer of small grain size in a desired film thickness by a lamination of polycrystalline materials.

摘要翻译： 在半导体衬底4上的氧化硅膜5上通过氧化硅膜5形成电极2时，例如，栅电极2被构成为多个多晶硅层6的叠层结构。 栅电极2的部分通过制造具有沉积非晶层的工艺的薄膜的方法和使该非晶材料结晶（再结晶）的方法形成。 在这种情况下，非晶层的沉积被分开多次进行，使得一次沉积的非晶层的厚度不大于根据根据下式确定的临界应力值规定的厚度 在每个非晶层的沉积过程完成之后，非晶材料结晶，重复沉积非晶层的过程和结晶非晶材料的过程，由此多晶层6的层压结构具有必要的 获得膜厚度。 利用上述结构，可以防止半导体器件的电特性的恶化和层之间的剥离等缺陷的发生，层中的裂纹等，并且可以获得 通过多晶材料的层叠，具有所需膜厚度的小晶粒尺寸的多晶层。