WORK FUNCTION TAILORING FOR NONVOLATILE MEMORY APPLICATIONS
    22.
    发明申请
    WORK FUNCTION TAILORING FOR NONVOLATILE MEMORY APPLICATIONS 有权
    用于非易失性存储器应用的工作功能定制

    公开(公告)号:US20120313069A1

    公开(公告)日:2012-12-13

    申请号:US13156624

    申请日:2011-06-09

    IPC分类号: H01L47/00

    摘要: Embodiments of the invention generally relate to a resistive switching nonvolatile memory device having an interface layer structure disposed between at least one of the electrodes and a variable resistance layer formed in the nonvolatile memory device, and a method of forming the same. Typically, resistive switching memory elements may be formed as part of a high-capacity nonvolatile memory integrated circuit, which can be used in various electronic devices, such as digital cameras, mobile telephones, handheld computers, and music players. In one configuration of the resistive switching nonvolatile memory device, the interface layer structure comprises a passivation region, an interface coupling region, and/or a variable resistance layer interface region that are configured to adjust the nonvolatile memory device's performance, such as lowering the formed device's switching currents and reducing the device's forming voltage, and reducing the performance variation from one formed device to another.

    摘要翻译: 本发明的实施例一般涉及具有设置在至少一个电极和形成在非易失性存储器件中的可变电阻层之间的界面层结构的电阻式开关非易失性存储器件及其形成方法。 通常,电阻式开关存储器元件可以形成为可用于各种电子设备(例如数码相机,移动电话,手持式计算机和音乐播放器)的大容量非易失性存储器集成电路的一部分。 在电阻式开关非易失性存储器件的一种结构中,界面层结构包括钝化区域,界面耦合区域和/或可变电阻层接口区域,其被配置为调整非易失性存储器件的性能,例如降低形成 器件的开关电流并降低器件的成型电压,并降低从一个成形器件到另一个器件的性能变化。

    Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate
    24.
    发明申请
    Methods of Combinatorial Processing for Screening Multiple Samples on a Semiconductor Substrate 有权
    在半导体基板上筛选多个样品的组合处理方法

    公开(公告)号:US20100001269A1

    公开(公告)日:2010-01-07

    申请号:US12167118

    申请日:2008-07-02

    IPC分类号: C23C16/00 H01L21/66 H01L23/58

    摘要: In embodiments of the current invention, methods of combinatorial processing and a test chip for use in these methods are described. These methods and test chips enable the efficient development of materials, processes, and process sequence integration schemes for semiconductor manufacturing processes. In general, the methods simplify the processing sequence of forming devices or partially formed devices on a test chip such that the devices can be tested immediately after formation. The immediate testing allows for the high throughput testing of varied materials, processes, or process sequences on the test chip. The test chip has multiple site isolated regions where each of the regions is varied from one another and the test chip is designed to enable high throughput testing of the different regions.

    摘要翻译: 在本发明的实施例中,描述了用于这些方法的组合处理方法和测试芯片。 这些方法和测试芯片能够有效地开发用于半导体制造工艺的材料,工艺和工艺顺序集成方案。 通常,这些方法简化了在测试芯片上形成器件或部分形成的器件的处理顺序,使得器件可以在形成后立即进行测试。 即时测试允许测试芯片上各种材料,工艺或工艺顺序的高通量测试。 测试芯片具有多个位置隔离区域,其中每个区域彼此变化,并且测试芯片被设计为能够实现不同区域的高通量测试。

    Method of depositing a copper seed layer which promotes improved feature surface coverage
    25.
    发明授权
    Method of depositing a copper seed layer which promotes improved feature surface coverage 有权
    沉积铜种子层的方法,其促进改进的特征表面覆盖

    公开(公告)号:US06500762B2

    公开(公告)日:2002-12-31

    申请号:US10056751

    申请日:2002-01-24

    IPC分类号: H01L2144

    摘要: We have discovered a method of improving step coverage of a copper seed layer deposited over a semiconductor feature surface which is particularly useful for small size features having a high aspect ratio. We have demonstrated that it is possible to increase the copper seed layer coverage simultaneously at the bottom of a high aspect ratio contact via and on the walls of the via by increasing the percentage of the depositing copper species which are ions. The percentage of species ionization which is necessary to obtain sufficient step coverage for the copper seed layer is a function of the aspect ratio of the feature. An increase in the percentage of copper species which are ionized can be achieved using techniques known in the art, including but not limited to applicants' preferred technique, an inductively coupled RF ion metal plasma.

    摘要翻译: 我们已经发现了一种改进沉积在半导体特征表面上的铜籽晶层的台阶覆盖率的方法,该方法对于具有高纵横比的小尺寸特征特别有用。 我们已经证明,可以通过增加作为离子的沉积铜物质的百分比,在高纵横比接触通孔和通孔的壁上同时增加铜种子层覆盖。 获得铜种子层足够的阶梯覆盖所必需的物质电离的百分比是该特征的纵横比的函数。 可以使用本领域已知的技术来实现电离的铜物质的百分比的增加,包括但不限于申请人的优选技术,电感耦合RF离子金属等离子体。

    Embedded nonvolatile memory elements having resistive switching characteristics
    26.
    发明授权
    Embedded nonvolatile memory elements having resistive switching characteristics 有权
    具有电阻开关特性的嵌入式非易失性存储元件

    公开(公告)号:US09129894B2

    公开(公告)日:2015-09-08

    申请号:US13621371

    申请日:2012-09-17

    摘要: Provided are nonvolatile memory assemblies each including a resistive switching layer and current steering element. The steering element may be a transistor connected in series with the switching layer. Resistance control provided by the steering element allows using switching layers requiring low switching voltages and currents. Memory assemblies including such switching layers are easier to embed into integrated circuit chips having other low voltage components, such as logic and digital signal processing components, than, for example, flash memory requiring much higher switching voltages. In some embodiments, provided nonvolatile memory assemblies operate at switching voltages less than about 3.0V and corresponding currents less than 50 microamperes. A memory element may include a metal rich hafnium oxide disposed between a titanium nitride electrode and doped polysilicon electrode. One electrode may be connected to a drain or source of the transistor, while another electrode is connected to a signal line.

    摘要翻译: 提供了各自包括电阻式开关层和电流控制元件的非易失性存储器组件。 转向元件可以是与开关层串联连接的晶体管。 由转向元件提供的电阻控制允许使用需要低开关电压和电流的开关层。 包括这种开关层的存储器组件比例如需要高得多的开关电压的闪速存储器更容易嵌入到具有其它低电压组件(例如逻辑和数字信号处理组件)的集成电路芯片中。 在一些实施例中,所提供的非易失性存储器组件在小于约3.0V的开关电压和小于50微安的相应电流下工作。 存储元件可以包括设置在氮化钛电极和掺杂多晶硅电极之间的富含金属的氧化铪。 一个电极可以连接到晶体管的漏极或源极,而另一个电极连接到信号线。