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218 条记录 (耗时 0.033 秒)

    Method for reducing surface defects in an electrodeposition process
    22.
    发明授权
    Method for reducing surface defects in an electrodeposition process 失效
    减少电沉积过程中表面缺陷的方法

    公开(公告)号：US06797144B2

    公开(公告)日：2004-09-28

    申请号：US10141277

    申请日：2002-05-08

    申请人： Hung-Wen Su ,  Shih-Wei Chou ,  Ching-Hua Hsieh ,  Shau-Lin Shue

    发明人： Hung-Wen Su ,  Shih-Wei Chou ,  Ching-Hua Hsieh ,  Shau-Lin Shue

    IPC分类号： C25D712

    CPC分类号： H01L21/2885 ,  C25D7/123 ,  H01L21/76877

    摘要： A method for in-situ cleaning an electrodeposition surface following an electroplating process including providing a first electrode assembly and a second electrode assembly; applying a first current density across the first electrode assembly and the second electrode assembly for carrying out the electrodeposition process; carrying out the electrodeposition process to electrodeposit a metal onto an electrodeposition surface of the second electrode assembly; and, applying a second current density having a second polarity reversed with reference to the first polarity across the first electrode assembly and the second electrode assembly the second current density having a relatively lower current density compared to the first current density.

    摘要翻译： 一种用于在电镀工艺之后原位清洁电沉积表面的方法，包括提供第一电极组件和第二电极组件; 在第一电极组件和第二电极组件上施加第一电流密度以执行电沉积过程; 执行电沉积工艺以将金属电沉积到第二电极组件的电沉积表面上; 并且相对于第一电流密度，第二电流密度具有相对于第一极性反转的第二电流密度跨越第一电极组件和第二电极组件，第二电流密度具有相对较低的电流密度。

    Loadlock
    24.
    发明申请
    Loadlock 审中-公开
    负载锁

    公开(公告)号：US20050097769A1

    公开(公告)日：2005-05-12

    申请号：US10668291

    申请日：2003-09-24

    申请人： Jing-Cheng Lin ,  Shing-Chyang Pan ,  Hsien-Ming Lee ,  Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai ,  Shau-Lin Shue

    发明人： Jing-Cheng Lin ,  Shing-Chyang Pan ,  Hsien-Ming Lee ,  Hung-Wen Su ,  Shih-Wei Chou ,  Ming-Hsing Tsai ,  Shau-Lin Shue

    IPC分类号： H01L21/677 ,  F26B13/30

    CPC分类号： H01L21/67781

    摘要： A loadlock. The loadlock for wafers includes a chamber, a pedestal, a retractable shaft, and a bellows. The chamber has a plurality of walls and a bottom surface. The pedestal supports a cassette and is disposed in the chamber. The retractable shaft has a top end and a bottom end. The top end is connected to the pedestal and the bottom end is connected to the bottom surface as a reference for positioning the pedestal. The bellows has a first end and a second end. The first end is disposed on the pedestal and the second end is sealed at the bottom end of the retractable shaft. Preferably, the retractable shaft is fully enclosed by the bellows.

    摘要翻译： 一个加载锁 用于晶片的负荷锁包括一个腔室，一个基座，一个伸缩轴和一个波纹管。 腔室具有多个壁和底面。 基座支撑盒并设置在腔室中。 伸缩轴具有顶端和底端。 顶端连接到基座，底端连接到底面作为基座的基准。 波纹管具有第一端和第二端。 第一端设置在基座上，第二端在可伸缩轴的底端被密封。 优选地，可伸缩轴被波纹管完全包围。

    Air gap for interconnect application
    28.
    发明授权
    Air gap for interconnect application 有权
    互连应用的气隙

    公开(公告)号：US07682963B2

    公开(公告)日：2010-03-23

    申请号：US11867308

    申请日：2007-10-04

    申请人： Hai-Ching Chen ,  Sunil Kumar Singh ,  Tien-I Bao ,  Shau-Lin Shue ,  Chen-Hua Yu

    发明人： Hai-Ching Chen ,  Sunil Kumar Singh ,  Tien-I Bao ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC分类号： H01L21/4763

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a method for fabricating an integrated circuit. The method includes forming an energy removable film (ERF) on a substrate; forming a first dielectric layer on the ERF; patterning the ERF and first dielectric layer to form a trench in the ERF and the first dielectric layer; filling a conductive material in the trench; forming a ceiling layer on the first dielectric layer and conductive material filled in the trench; and applying energy to the ERF to form air gaps in the ERF after the forming of the ceiling layer.

    摘要翻译： 本公开提供了一种用于制造集成电路的方法。 该方法包括在基板上形成能量可去除膜（ERF）; 在ERF上形成第一介电层; 图案化ERF和第一介电层以在ERF和第一介电层中形成沟槽; 在沟槽中填充导电材料; 在第一介电层上形成顶层和填充在沟槽中的导电材料; 并且在形成天花板层之后，向ERF施加能量以在ERF中形成气隙。

    AIR GAP FOR INTERCONNECT APPLICATION
    29.
    发明申请
    AIR GAP FOR INTERCONNECT APPLICATION 有权
    用于互连应用的空气隙

    公开(公告)号：US20090091038A1

    公开(公告)日：2009-04-09

    申请号：US11867308

    申请日：2007-10-04

    申请人： Hai-Ching Chen ,  Sunil Kumar Singh ,  Tien-I Bao ,  Shau-Lin Shue ,  Chen-Hua Yu

    发明人： Hai-Ching Chen ,  Sunil Kumar Singh ,  Tien-I Bao ,  Shau-Lin Shue ,  Chen-Hua Yu

    IPC分类号： H01L23/52 ,  H01L21/4763

    CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a method for fabricating an integrated circuit. The method includes forming an energy removable film (ERF) on a substrate; forming a first dielectric layer on the ERF; patterning the ERF and first dielectric layer to form a trench in the ERF and the first dielectric layer; filling a conductive material in the trench; forming a ceiling layer on the first dielectric layer and conductive material filled in the trench; and applying energy to the ERF to form air gaps in the ERF after the forming of the ceiling layer.

    摘要翻译： 本公开提供了一种用于制造集成电路的方法。 该方法包括在基板上形成能量可去除膜（ERF）; 在ERF上形成第一介电层; 图案化ERF和第一介电层以在ERF和第一介电层中形成沟槽; 在沟槽中填充导电材料; 在第一介电层上形成顶层和填充在沟槽中的导电材料; 并且在形成天花板层之后，向ERF施加能量以在ERF中形成气隙。

    Sidewall coverage for copper damascene filling
    30.
    发明授权
    Sidewall coverage for copper damascene filling 有权
    铜镶嵌填料的侧壁覆盖

    公开(公告)号：US07282450B2

    公开(公告)日：2007-10-16

    申请号：US10733722

    申请日：2003-12-11

    申请人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    发明人： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

    摘要： A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

    摘要翻译： 描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。 具体应用是用铜填充沟槽以形成镶嵌线。 首先，通过PVD将种子层沉积在孔或沟槽中。 然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。 描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。