公开(公告)号：US20240113026A1

公开(公告)日：2024-04-04

申请号：US18526127

申请日：2023-12-01

Applicant: Infineon Technologies AG

Inventor： Edward Fürgut ,  Ravi Keshav Joshi ,  Thomas Basler ,  Martin Gruber ,  Jochen Hilsenbeck ,  Wolfgang Scholz

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/00 ,  H01L29/16 ,  H01L29/45

CPC classification number: H01L23/53238 ,  H01L21/7685 ,  H01L24/45 ,  H01L29/1608 ,  H01L29/45 ,  H01L2224/05172 ,  H01L2224/05179 ,  H01L2224/05181 ,  H01L2224/05672 ,  H01L2224/05679 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147

Abstract: A silicon carbide device includes a silicon carbide substrate, a contact layer located on the silicon carbide substrate and including nickel and silicon, a barrier layer structure including titanium and tungsten, and a metallization layer comprising copper, wherein the contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure, wherein the barrier layer structure is located between the silicon carbide substrate and the metallization layer, wherein the metallization layer is configured as a contact pad of the silicon carbide device.

公开(公告)号：US11881512B2

公开(公告)日：2024-01-23

申请号：US17519161

申请日：2021-11-04

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Romain Esteve ,  Ravi Keshav Joshi ,  Shiqin Niu

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

CPC classification number: H01L29/1608 ,  H01L29/4236 ,  H01L29/66068 ,  H01L29/66348 ,  H01L29/66666 ,  H01L29/7802 ,  H01L29/7813 ,  H01L29/7827 ,  H01L29/7828

Abstract: A method includes providing a silicon carbide substrate, wherein a gate trench extends from a main surface of the silicon carbide substrate into the silicon carbide substrate and wherein a gate dielectric is formed on at least one sidewall of the gate trench, and forming a gate electrode in the gate trench, the gate electrode including a metal structure and a semiconductor layer between the metal structure and the gate dielectric.

公开(公告)号：US20230253454A1

公开(公告)日：2023-08-10

申请号：US18100144

申请日：2023-01-23

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Thomas Ralf Siemieniec ,  Werner Schustereder ,  Kristijan Luka Mletschnig ,  Axel König

IPC: H01L29/08 ,  H01L29/16 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/04 ,  H01L29/66

CPC classification number: H01L29/0869 ,  H01L29/1608 ,  H01L29/41741 ,  H01L29/45 ,  H01L29/7813 ,  H01L21/0475 ,  H01L21/0485 ,  H01L29/66068

Abstract: A method of manufacturing a semiconductor device includes forming a trench that extends from a first surface into a silicon carbide body. A first doped region and an oppositely doped second doped region are formed in the silicon carbide body. A lower layer structure is formed on a lower sidewall portion of the trench. An upper layer stack is formed on an upper sidewall portion and/or on the first surface. The first doped region and the upper layer stack are in direct contact along the upper sidewall portion and/or on the first surface. The second doped region and the lower layer structure are in direct contact along the lower sidewall portion.

公开(公告)号：US10777506B2

公开(公告)日：2020-09-15

申请号：US16577316

申请日：2019-09-20

Applicant: Infineon Technologies AG

Inventor： Frank Hille ,  Ravi Keshav Joshi ,  Michael Fugger ,  Oliver Humbel ,  Thomas Laska ,  Matthias Müller ,  Roman Roth ,  Carsten Schaeffer ,  Hans-Joachim Schulze ,  Holger Schulze ,  Juergen Steinbrenner ,  Frank Umbach

IPC: H01L23/532 ,  H01L23/485 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: According to an embodiment of a semiconductor device, the semiconductor devices includes a metal structure electrically connected to a silicon carbide semiconductor body and a metal adhesion and barrier structure between the metal structure and the silicon carbide semiconductor body. The metal adhesion and barrier structure includes a layer comprising titanium and tungsten.

公开(公告)号：US10256097B2

公开(公告)日：2019-04-09

申请号：US15846591

申请日：2017-12-19

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Romain Esteve ,  Roland Rupp ,  Francisco Javier Santos Rodriguez ,  Gerald Unegg

IPC: H01L21/04 ,  H01L29/06 ,  H01L29/10 ,  H01L29/45 ,  H01L29/66 ,  H01L29/732 ,  H01L29/808 ,  H01L29/861 ,  H01L29/417 ,  H01L29/423 ,  H01L29/08 ,  H01L29/78 ,  H01L29/16 ,  H01L29/739

Abstract: A semiconductor device includes a silicon carbide semiconductor body and a metal contact structure. Interface particles including a silicide kernel and a carbon cover on a surface of the silicide kernel are formed directly between the silicon carbide semiconductor body and the metal contact structure. Between neighboring ones of the interface particles, the metal contact structure directly adjoins the silicon carbide semiconductor body.

公开(公告)号：US20180076036A1

公开(公告)日：2018-03-15

申请号：US15582940

申请日：2017-05-01

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Romain Esteve ,  Markus Kahn ,  Kurt Pekoll ,  Juergen Steinbrenner ,  Gerald Unegg

IPC: H01L21/04 ,  H01L29/16 ,  H01L21/324 ,  H01L29/45 ,  H01L21/02

CPC classification number: H01L21/0485 ,  H01L21/0217 ,  H01L21/28518 ,  H01L21/324 ,  H01L21/76897 ,  H01L29/1608 ,  H01L29/45 ,  H01L29/66068 ,  H01L29/665 ,  H01L29/7802

Abstract: A silicon-carbide substrate that includes: a doped silicon-carbide contact region directly adjoining a main surface of the substrate, and a dielectric layer covering the main surface is provided. A protective layer is formed on the silicon-carbide substrate such that the protective layer covers the dielectric layer and exposes the doped silicon-carbide contact region at the main surface. A metal layer that conforms to the protective layer and directly contacts the exposed doped silicon-carbide contact region is deposited. A first rapid thermal anneal process is performed. A thermal budget of the first rapid thermal anneal process is selected to cause the metal layer to form a silicide with the doped silicon-carbide contact region during the first rapid thermal anneal process without causing the metal layer to form a silicide with the protective layer during the first rapid thermal anneal process.

公开(公告)号：US09773736B2

公开(公告)日：2017-09-26

申请号：US14607708

申请日：2015-01-28

Applicant: Infineon Technologies AG

Inventor： Ravi Keshav Joshi ,  Juergen Steinbrenner ,  Christian Fachmann ,  Petra Fischer ,  Roman Roth

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/00 ,  H01L21/3213

CPC classification number: H01L23/53238 ,  H01L21/32134 ,  H01L21/32139 ,  H01L21/76885 ,  H01L24/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a metallization layer over a semiconductor substrate includes depositing a blanket layer of a diffusion barrier liner over an inter level dielectric layer, and depositing a blanket layer of an intermediate layer over the diffusion barrier liner. A blanket layer of a power metal layer including copper is deposited over the intermediate layer. The intermediate layer includes a solid solution of a majority element and copper. The intermediate layer has a different etch selectivity from the power metal layer. After depositing the power metal layer, structuring the power metal layer, the intermediate layer, and the diffusion barrier liner.

公开(公告)号：US20240055257A1

公开(公告)日：2024-02-15

申请号：US18360459

申请日：2023-07-27

Applicant: Infineon Technologies AG

Inventor： Saurabh Roy ,  Werner Schustereder ,  Ravi Keshav Joshi ,  Hans-Joachim Schulze ,  Daria Krasnozhon

IPC: H01L21/04 ,  H01L29/45 ,  H01L29/16 ,  H01L29/04

CPC classification number: H01L21/0485 ,  H01L29/452 ,  H01L29/1608 ,  H01L29/045

Abstract: The disclosure relates to a method for manufacturing a contact on a SiC substrate, wherein the method includes: providing a crystalline SiC substrate; modifying a crystal structure in a surface area of the SiC substrate such that a carbon-enriched SiC portion is generated in the surface area; forming a contact layer on the SiC substrate by depositing a metallic contact material onto the surface area that includes the carbon-enriched SiC portion; and thermal annealing of at least a part of the carbon-enriched SiC portion of the SiC substrate and at least a part of the contact layer, such that a ternary metallic phase portion including at least the metallic contact material, silicon, and carbon is generated. Furthermore, SiC semiconductor devices are described, which include a crystalline SiC substrate and a contact layer including a ternary metallic phase portion directly in contact with the SiC substrate surface.

公开(公告)号：US20220285283A1

公开(公告)日：2022-09-08

申请号：US17752224

申请日：2022-05-24

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Ravi Keshav Joshi ,  Ralf Siemieniec ,  Thomas Basler ,  Martin Gruber ,  Jochen Hilsenbeck ,  Dethard Peters ,  Roland Rupp ,  Wolfgang Scholz

IPC: H01L23/532 ,  H01L29/16 ,  H01L21/768 ,  H01L23/00 ,  H01L29/45

Abstract: A power semiconductor device includes a semiconductor substrate having a wide bandgap semiconductor material and a first surface, an insulation layer above the first surface of the semiconductor substrate, the insulation layer including at least one opening extending through the insulation layer in a vertical direction, a front metallization above the insulation layer with the insulation layer being interposed between the front metallization and the first surface of the semiconductor substrate, and a metal connection arranged in the opening of the insulation layer and electrically conductively connecting the front metallization with the semiconductor substrate; wherein the front metallization includes at least one layer that is a metal or a metal alloy having a higher melting temperature than an intrinsic temperature of the wide bandgap semiconductor material of the semiconductor substrate.

公开(公告)号：US20220059659A1

公开(公告)日：2022-02-24

申请号：US17519161

申请日：2021-11-04

Applicant: Infineon Technologies AG

Inventor： Ralf Siemieniec ,  Thomas Aichinger ,  Romain Esteve ,  Ravi Keshav Joshi ,  Shiqin Niu

IPC: H01L29/16 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: A method includes providing a silicon carbide substrate, wherein a gate trench extends from a main surface of the silicon carbide substrate into the silicon carbide substrate and wherein a gate dielectric is formed on at least one sidewall of the gate trench, and forming a gate electrode in the gate trench, the gate electrode including a metal structure and a semiconductor layer between the metal structure and the gate dielectric.