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公开(公告)号：US20210271305A1
公开(公告)日：2021-09-02
申请号：US17183518
申请日：2021-02-24
Applicant: Intel Corporation
Inventor： Alexander Gendler , Igor Yanover , Gavri Berger , Edo Hachamo , Elkana Korem , Hanan Shomroni , Daniela Kaufman , Lev Makovsky , Haim Granot
IPC: G06F1/324 , G06F1/3206
Abstract: In an embodiment, a processor includes processing cores to execute instructions; and throttling logic. The throttling logic is to: determine an average capacitance score for execution events in a sliding window; perform frequency throttling when the average capacitance score exceeds a throttling threshold; determine a count of frequency throttling instances; and in response to a determination that the count of frequency throttling instances exceeds a maximum throttling value, increase the throttling threshold and concurrently reduce a baseline frequency. Other embodiments are described and claimed.
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公开(公告)号：US10663998B1
公开(公告)日：2020-05-26
申请号：US16370510
申请日：2019-03-29
Applicant: Intel Corporation
Inventor： Tamir Salus , Alexander Lyakhov , Alexander Gendler , Krishnakanth Sistla , Ankush Varma , Rachid Rayess , Nimrod Angel
Abstract: Various embodiments provide a voltage regulator circuit with automatic phase shedding. A control circuit may control first transitions of a power state of the voltage regulator based on an average current draw of the voltage regulator. The control circuit may further control second transitions of the power state of the voltage regulator based on a voltage droop of the output voltage and/or a peak current draw of the voltage regulator. The first transitions may be performed synchronously, and the second transitions may be performed asynchronously. Other embodiments may be described and claimed.
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23.发明授权公开(公告)号：US10437315B2
公开(公告)日：2019-10-08
申请号：US15629872
申请日：2017-06-22
Applicant: Intel Corporation
Inventor： Alexander Gendler , Arkady Bramnik , Lev Makovsky
IPC: G06F1/32 , G06F1/3287 , G06F11/10 , G06F1/324 , G06F1/3234 , G06F1/3296
Abstract: In one embodiment, a processor core has one or more execution units, a first memory array having a first protection circuit to provide soft error protection to the first memory array, and a control circuit. A power controller coupled to the core may include a protection control circuit, in response to an update to an operating voltage to be provided to the core, to cause the core to disable the first protection circuit. Other embodiments are described and claimed.
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公开(公告)号：US10126775B2
公开(公告)日：2018-11-13
申请号：US15448332
申请日：2017-03-02
Applicant: Intel Corporation
Inventor： Alexander Gendler , Kosta Luria , Arye Albahari , Ohad Nachshon
Abstract: A method and apparatus for performing current control for an integrated circuit are described. In one embodiment the apparatus comprises core logic coupled to receive a first current; a clock generator to generate a first clock signal; and a closed loop current controller coupled to the clock generator and coupled to provide a second clock signal to the core logic based on the first clock signal, the current controller to control an amount of the first current received by the core logic by changing the first clock signal to generate the second clock signal.
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公开(公告)号：US20180173298A1
公开(公告)日：2018-06-21
申请号：US15381611
申请日：2016-12-16
Applicant: Intel Corporation
Inventor： Alexander Gendler , Boris Mishori , Krishnakanth V. Sistla , Ankush Varma , Avinash N. Ananthakrishnan , Lev Makovsky , Michael Zelikson , Eran Altshuler , Israel Stolero
CPC classification number: G06F1/3296 , G06F1/206 , G06F1/3206 , G06F1/324
Abstract: An apparatus is provided, comprising: a first circuitry configured to generate a signal at a voltage level for one or more components; a second circuitry configured to generate a clock at a frequency level for the one or more components; a third circuitry configured to intermittently measure a current level of the signal; a fourth circuitry configured to estimate a first average of the current level of the signal over a first time-window; and a fifth circuitry configured to, in response to the first average being higher than a threshold average current, facilitate regulating one or both the voltage level of the signal or the frequency level of the clock.
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Patent Agency Ranking
公开(公告)号：US09891695B2
公开(公告)日：2018-02-13
申请号：US14751889
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Alexander Gendler , Ariel Berkovits , Michael Mishaeli , Nadav Shulman , Sameer Desai , Shani Rehana , Ittai Anati , Hisham Shafi
IPC: G06F1/32 , G06F12/08 , G06F12/14 , G06F12/0868 , G06F12/0804 , G06F12/0888
CPC classification number: G06F1/3287 , G06F12/0804 , G06F12/0868 , G06F12/0888 , G06F12/1433 , G06F2212/1052 , G06F2212/311 , G06F2212/621
Abstract: A method and apparatus for flushing and restoring core memory content to and from, respectively, external memory are described. In one embodiment, the apparatus is an integrated circuit comprising a plurality of processor cores, the plurality of process cores including one core having a first memory operable to store data of the one core, the one core to store data from the first memory to a second memory located externally to the processor in response to receipt of a first indication that the one core is to transition from a first low power idle state to a second low power idle state and receipt of a second indication generated externally from the one core indicating that the one core is to store the data from the first memory to the second memory, locations in the second memory at which the data is stored being accessible by the one core and inaccessible by other processor cores in the IC; and a power management controller coupled to the plurality of cores and located outside the plurality of cores.
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公开(公告)号：US09772678B2
公开(公告)日：2017-09-26
申请号：US15139455
申请日：2016-04-27
Applicant: Intel Corporation
Inventor： Ruchira Sasanka , Alexander Gendler , Udi Sherel
IPC: G06F1/32 , G06F1/26 , G06F12/02 , G06F12/084
CPC classification number: G06F1/3296 , G06F1/266 , G06F1/324 , G06F12/0223 , G06F12/084 , G06F2212/62 , Y02D10/126 , Y02D10/172 , Y02D50/20
Abstract: In an embodiment, a processor includes one or more cores including a first core operable at an operating voltage between a minimum operating voltage and a maximum operating voltage. The processor also includes a power control unit including first logic to enable coupling of ancillary logic to the first core responsive to the operating voltage being less than or equal to a threshold voltage, and to disable the coupling of the ancillary logic to the first core responsive to the operating voltage being greater than the threshold voltage. Other embodiments are described and claimed.
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公开(公告)号：US09710041B2
公开(公告)日：2017-07-18
申请号：US14812056
申请日：2015-07-29
Applicant: Intel Corporation
Inventor： Alexander Gendler , Larisa Novakovsky , Krishnakanth V. Sistla , Vivek Garg , Dean Mulla , Ashish V. Choubal , Erik G. Hallnor , Kimberly C. Weier
CPC classification number: G06F1/3203 , G06F1/04 , G06F1/26 , G06F1/263 , G06F1/3237 , G06F1/324 , G06F1/3243 , G06F1/329 , G06F1/3293 , G06F9/38 , G06F15/163 , G06F15/17 , Y02D10/122 , Y02D10/126 , Y02D10/128 , Y02D10/152 , Y02D10/24 , Y02D50/20
Abstract: In one embodiment, a processor includes a core to execute instructions and a core perimeter logic coupled to the core. The core perimeter logic may include a fabric interface logic coupled to the core. In turn, the fabric interface logic may include a first storage to store state information of the core when the core is in a low power state, and enable an inter-die interconnect coupled between the core and an uncore to be maintained in an active state during entry of the core into a low power state. Other embodiments are described and claimed.
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公开(公告)号：US20170177022A1
公开(公告)日：2017-06-22
申请号：US15448332
申请日：2017-03-02
Applicant: Intel Corporation
Inventor： Alexander Gendler , Kosta Luria , Arye Albahari , Ohad Nachshon
IPC: G06F1/08 , G06F1/26 , G01R19/165 , G06F1/06
CPC classification number: G06F1/08 , G01R1/203 , G01R19/0092 , G01R19/16528 , G01R19/16533 , G06F1/06 , G06F1/26
Abstract: A method and apparatus for performing current control for an integrated circuit are described. In one embodiment the apparatus comprises core logic coupled to receive a first current; a clock generator to generate a first clock signal; and a closed loop current controller coupled to the clock generator and coupled to provide a second clock signal to the core logic based on the first clock signal, the current controller to control an amount of the first current received by the core logic by changing the first clock signal to generate the second clock signal.
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公开(公告)号：US20170168541A1
公开(公告)日：2017-06-15
申请号：US14969561
申请日：2015-12-15
Applicant: Intel Corporation
Inventor： Alexander Gendler
IPC: G06F1/32
CPC classification number: G06F1/324 , G06F1/3206 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: Methods and apparatus relating to techniques for processor core energy management are described. In an embodiment, energy management logic causes a modification to energy consumption by an electrical load (such as a processor core) based at least in part on comparison of an electrical current value and an operating current threshold value. The electrical current value is detected at an electrical current sensor coupled to the electrical load. Other embodiments are also disclosed and claimed.
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