公开(公告)号：US09755449B2

公开(公告)日：2017-09-05

申请号：US14495930

申请日：2014-09-25

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  Alexander B. Uan-Zo-Li ,  Robert A. Dunstan

IPC: H02J7/00 ,  G06F13/40

CPC classification number: H02J7/0052 ,  G06F13/4022 ,  H02J2007/0059 ,  H02J2007/0062 ,  H02J2007/0096

Abstract: Systems and methods may provide for a charger that includes a converter with a battery port, a first bypass switch coupled to a first bus port and the battery port, and a second bypass switch coupled to a second bus port and the battery port. Additionally, a charge controller may use one or more control signals to manage power to be delivered from the first bus port through the first bypass switch to the battery port, and power to be delivered from the second bus port through the second bypass switch to the battery port.

公开(公告)号：US09558144B2

公开(公告)日：2017-01-31

申请号：US14497925

申请日：2014-09-26

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  Tod Schiff ,  Vijayakumar Dibbad ,  Alan Hallberg

IPC: G06F3/00 ,  G06F13/42 ,  G06F13/38 ,  G06F13/40

CPC classification number: G06F13/385 ,  G06F13/382 ,  G06F13/4068 ,  G06F13/4282

Abstract: Some embodiments include apparatuses and methods having a node to couple to a serial bus, and a controller to provide a control signal to one of a first circuit path and a second circuit path in order to change electrical termination of a signal at the node between a first electrical termination through the first circuit path during a first mode of the controller and a second electrical termination through the second circuit path during a second mode of the controller. The controller can be arranged to provide the control signal to the first and second circuit paths during the first and second modes without providing another control signal from the controller to the first and second circuit paths during the first and second modes.

Abstract translation: 一些实施例包括具有耦合到串行总线的节点的装置和方法，以及控制器，以向第一电路路径和第二电路路径之一提供控制信号，以便改变位于第一电路路径和第二电路路径之间的节点处的信号的电终端 在控制器的第一模式期间通过第一电路路径进行第一电终接，并且在控制器的第二模式期间通过第二电路路径进行第二电终接。 控制器可以被布置为在第一和第二模式期间向第一和第二电路路径提供控制信号，而不在第一和第二模式期间从控制器向第一和第二电路路径提供另一个控制信号。

公开(公告)号：US12181947B2

公开(公告)日：2024-12-31

申请号：US17030175

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Chee Lim Nge ,  Alexander Uan-Zo-li ,  Zhongsheng Wang ,  James Hermerding, II ,  Caren Magi

IPC: G06F1/3212 ,  G06F1/32 ,  G06F1/3234

Abstract: A driver (e.g., a firmware or software) that improves the performance of the system-on-chip (SoC) in battery mode. The driver is a Peak Power Manager (PPM) which allows drastically higher SoC peak power limit levels (and thus higher Turbo performance) in battery mode. The PPM sets the Vth threshold voltage (the voltage level at which the platform will throttle the SoC) in such a way as to prevent the system from unexpected shutdown (or black screening). The PPM calculates the Psoc,pk SoC Peak Power Limit (e.g., PL4), according to the threshold voltage (Vth). These are two dependent parameters, if one is set, the other can be calculated. The scheme by the PPM is used to optimally set one parameter (Vth) based on the system parameters, and the history of the operation.

公开(公告)号：US12079051B2

公开(公告)日：2024-09-03

申请号：US17832370

申请日：2022-06-03

Applicant: Intel Corporation

Inventor： Naoki Matsumura ,  Tod F. Schiff ,  Brian Fritz ,  Chee Lim Nge ,  Jorge Rodriguez

IPC: G06F1/20 ,  G06F1/26 ,  H01M10/617 ,  H01M10/63 ,  H02J7/00

CPC classification number: G06F1/206 ,  G06F1/26 ,  H01M10/617 ,  H01M10/63 ,  H02J7/0063

Abstract: Techniques are provided for operating a computing system in a peak power mode while avoiding increased degradation of a battery. The peak power mode include cycles with peak and off-peak currents. The amplitude and duration of the peak and off-peak currents are governed by a thermal/heat budget of the battery. A processor can read the battery information during usage and calculate one or more parameters which are derived from heat. If a parameter is smaller than a reference value, the processor can update the peak power parameters to provide an increase in peak current/power and/or duration. If a parameter is larger than the reference value, no heat budget is available to provide an increase in peak current/power and/or duration. The thermal/heat budget can be enforced over each cycle of the peak power mode or in a summation over multiple cycles.

公开(公告)号：US11972303B2

公开(公告)日：2024-04-30

申请号：US16914177

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Carin Ruiz ,  Bo Qiu ,  Columbia Mishra ,  Arijit Chattopadhyay ,  Chee Lim Nge ,  Srikanth Potluri ,  Jianfang Zhu ,  Deepak Samuel Kirubakaran ,  Akhilesh Rallabandi ,  Mark Gallina ,  Renji Thomas ,  James Hermerding, II

IPC: G06F9/50 ,  G06F9/48 ,  G06F11/30

CPC classification number: G06F9/5094 ,  G06F9/4881 ,  G06F9/505 ,  G06F11/3058 ,  G06F2209/508

Abstract: Methods, apparatus, and systems to dynamically schedule a workload to among compute blocks based on temperature are disclosed. An apparatus to schedule a workload to at least one of a plurality of compute blocks based on temperature includes a prediction engine to determine (i) a first predicted temperature of a first compute block of the plurality of compute blocks and (ii) a second predicted temperature of a second compute block of the plurality of compute blocks. The apparatus also includes a selector to select between the first compute block and the second compute block for assignment of the workload. The selection is based on which of the first and second predicted temperatures is lower. The apparatus further includes a workload scheduler to assign the workload to the selected one of the first or second compute blocks.

公开(公告)号：US11775047B2

公开(公告)日：2023-10-03

申请号：US17879256

申请日：2022-08-02

Applicant: INTEL CORPORATION

Inventor： Jianfang Zhu ,  Deepak Samuel Kirubakaran ,  Raoul Rivas Toledano ,  Chee Lim Nge ,  Rajshree Chabukswar ,  James Hermerding, II ,  Sudheer Nair ,  William Braun ,  Zhongsheng Wang ,  Russell Fenger ,  Udayan Kapaley

IPC: G06F1/32 ,  G06F1/329 ,  G06F1/3228 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F1/329 ,  G06F1/3228 ,  G06F9/3836 ,  G06F9/4812 ,  G06F9/4893

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

公开(公告)号：US20220407337A1

公开(公告)日：2022-12-22

申请号：US17354944

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Zhongsheng Wang ,  Chee Lim Nge ,  Sze Ling Yeap ,  Efraim Rotem ,  James Hermerding II ,  Ashraf Wadaa

IPC: H02J7/00

Abstract: A hardware and/or software (e.g., a controller and/or firmware or software) that monitors a remaining capacity of a battery and adjusts a continuum of system performance settings ranging from best performance to best energy efficiency. The controller starts with best performance setting (at the expense of energy efficiency), and then the controller gradually shifts toward energy efficiency setting (at the expense of performance) when a battery usage exceeds a pre-defined drain rate (e.g., there is a deficit in the battery remaining capacity until the next charge). The controller reverts from energy efficiency setting towards high performance setting when the battery drain rate or discharge rate slows down (e.g., there is a surplus in the battery remaining capacity until the next charge).

公开(公告)号：US20220374066A1

公开(公告)日：2022-11-24

申请号：US17879256

申请日：2022-08-02

Applicant: INTEL CORPORATION

Inventor： JIANFANG ZHU ,  Deepak Samuel Kirubakaran ,  Raoul Rivas Toledano ,  Chee Lim Nge ,  Rajshree Chabukswar ,  James Hermerding, II ,  Sudheer Nair ,  William Braun ,  Zhongsheng Wang ,  Russell Fenger ,  Udayan Kapaley

IPC: G06F1/329 ,  G06F1/3228 ,  G06F9/38 ,  G06F9/48

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

公开(公告)号：US11476692B2

公开(公告)日：2022-10-18

申请号：US16831933

申请日：2020-03-27

Applicant: INTEL CORPORATION

Inventor： Anil Baby ,  Alexander B. Uan-Zo-li ,  Chee Lim Nge ,  N V S Kumar Srighakollapu

IPC: H02J7/00 ,  H02J7/34 ,  G06F1/3218 ,  G06F1/30

Abstract: In some examples, an apparatus includes a battery and a dynamic voltage source coupled in series with the battery. The dynamic voltage source is to maintain (or clamp) a system voltage from going below a minimum system voltage.

公开(公告)号：US11449127B2

公开(公告)日：2022-09-20

申请号：US16642694

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Eugene Gorbatov ,  Alexander Uan-Zo-Li ,  Chee Lim Nge ,  James Hermerding, II ,  Zhongsheng Wang

IPC: G06F1/00 ,  G06F1/3296 ,  G06F1/28

Abstract: Peak power setting circuitry is provided to set a peak power value for an integrated circuit device. A power supply interface is to receive a value to estimate a peak power capacity of a power supply serving the integrated circuit device and processing circuitry is provided to calculate an approximate peak power for the integrated circuit device. A peak power for the integrated circuit device is determined by increasing the approximate peak power depending on an amount by which the integrated circuit device power is reduced in response to assertion of a throttling signal.