公开(公告)号：US20200373329A1

公开(公告)日：2020-11-26

申请号：US16989430

申请日：2020-08-10

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Clifford Lu Ong ,  Ian A. Young

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L27/11592 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  G06N3/063

Abstract: Disclosed herein are neural computing dies with stacked neural core regions as well as related methods and assemblies. In some embodiments, a neural computing die may include: a first neural core region; a second neural core region; and an inter-core interconnect region in a volume between the first neural core region and the second neural core region, wherein the inter-core interconnect region includes a conductive pathway between the first neural core region and the second neural core region, and the conductive pathway includes a conductive via.

公开(公告)号：US10679782B2

公开(公告)日：2020-06-09

申请号：US15751111

申请日：2015-09-09

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Dmitri E. Nikonov ,  Anurag Chaudhry ,  Ian A. Young

IPC: G11C11/16 ,  G11C11/18 ,  H01L43/00 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12 ,  H01F10/32 ,  H03K19/18 ,  H03K19/23 ,  H01F41/32 ,  H01L27/22

Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a first spin current; a first layer configured to convert the first spin current to a second charge current via spin orbit coupling (SOC), wherein at least a part of the first layer is coupled to the input ferromagnet; and a second layer configured to convert the second charge current to a second spin current via spin orbit coupling (SOC).

公开(公告)号：US10483455B2

公开(公告)日：2019-11-19

申请号：US14778704

申请日：2013-06-29

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Ian A. Young

IPC: H01L29/82 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12 ,  G11C11/16

Abstract: An embodiment includes a magnetic tunnel junction (MTJ) having a non-elliptical free layer with rounded corners. For example, an embodiment includes a MTJ including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers; wherein the free magnetic layer includes a top surface, a bottom surface, and a sidewall circumnavigating the free magnetic layer and coupling the bottom surface to the top surface; wherein the top surface is rectangular with a plurality of rounded corners. In an embodiment, the aspect ratio of the top surface is between 4:1 and 8:1 (length to width). Such an embodiment provides ease of manufacture along with accept critical switching current (to reverse polarity of the free layer) and stability. Other embodiments are described herein.

公开(公告)号：US10483026B2

公开(公告)日：2019-11-19

申请号：US15569978

申请日：2015-06-24

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Anurag Chaudhry ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: G11C11/00 ,  H01F10/32 ,  H01L43/10 ,  H01L43/08 ,  H03K19/16 ,  G11C11/16 ,  G11C11/155 ,  H03K19/18 ,  H01F10/26

Abstract: Described is an apparatus which comprises: an input ferromagnet to receive a first charge current and to produce a corresponding spin current; and a stack of metal layers configured to convert the corresponding spin current to a second charge current, wherein the stack of metal layers is coupled to the input magnet.

公开(公告)号：US20180331281A1

公开(公告)日：2018-11-15

申请号：US16046189

申请日：2018-07-26

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Elijah Ilya Karpov ,  Brian Doyle ,  Dmitri E. Nikonov ,  Ian Young

IPC: H01L45/00 ,  G11C14/00 ,  G11C11/16 ,  H01L27/24 ,  H01L27/02 ,  G11C13/00 ,  G11C11/00 ,  G11C8/16 ,  G06F12/02

CPC classification number: H01L45/00 ,  G06F12/0246 ,  G06F2212/7201 ,  G11C8/16 ,  G11C11/005 ,  G11C11/16 ,  G11C13/0007 ,  G11C13/0026 ,  G11C14/0018 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/0207 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146

Abstract: Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.

公开(公告)号：US20180240964A1

公开(公告)日：2018-08-23

申请号：US15751102

申请日：2015-09-10

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Sasikanth Manipatruni ,  Anurag Chaudhry ,  Ian A. Young

IPC: H01L43/04 ,  H01L43/08 ,  H01L43/10 ,  H01L43/06 ,  H03K19/18

CPC classification number: H01L43/04 ,  H01L43/065 ,  H01L43/08 ,  H01L43/10 ,  H03K19/18

Abstract: Described is an apparatus which comprises: a first non-magnetic conductor; a first spin orbit coupling (SOC) layer coupled to the first non-magnetic conductor; a first ferromagnet (FM) coupled to the SOC layer; a second FM; and an insulating FM sandwiched between the first and second FMs.

公开(公告)号：US10043971B2

公开(公告)日：2018-08-07

申请号：US14546061

申请日：2014-11-18

Applicant: Intel Corporation

Inventor： Sasikanth Manipatruni ,  Elijah Ilya Karpov ,  Brian Doyle ,  Dmitri E. Nikonov ,  Ian Young

IPC: H01L45/00 ,  G06F12/02 ,  G11C14/00 ,  G11C11/16 ,  G11C8/16 ,  G11C11/00 ,  G11C13/00 ,  H01L27/02 ,  H01L27/24

Abstract: Some embodiments include apparatuses and methods having a memory element included in a non-volatile memory cell, a transistor, an access line coupled to a gate to the transistor, a first conductive line, and a second conductive line. The memory element can include a conductive oxide material located over a substrate and between the first and second conductive lines. The memory element includes a portion coupled to a drain of the transistor and another portion coupled to the second conductive line. The first conductive line is coupled to a source of the transistor and can be located between the access line and the memory element. The access line has a length extending in a first direction and can be located between the substrate and the memory element. The first and second conductive lines have lengths extending in a second direction.

公开(公告)号：US20160133699A1

公开(公告)日：2016-05-12

申请号：US14942274

申请日：2015-11-16

Applicant: Intel Corporation

Inventor： Uygar E. Avci ,  Dmitri E. Nikonov ,  Ian A. Young

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/267 ,  H01L29/775 ,  H01L29/165 ,  H01L29/205 ,  H01L29/08

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L29/068 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/205 ,  H01L29/267 ,  H01L29/7391 ,  H01L29/772 ,  H01L29/775

Abstract: An embodiment includes a heterojunction tunneling field effect transistor including a source, a channel, and a drain; wherein (a) the channel includes a major axis, corresponding to channel length, and a minor axis that corresponds to channel width and is orthogonal to the major axis; (b) the channel length is less than 10 nm long; (c) the source is doped with a first polarity and has a first conduction band; (d) the drain is doped with a second polarity, which is opposite the first polarity, and the drain has a second conduction band with higher energy than the first conduction band. Other embodiments are described herein.

Abstract translation: 一个实施例包括一个包括源极，沟道和漏极的异质结隧道场效应晶体管; 其中（a）所述通道包括对应于通道长度的长轴和对应于通道宽度并与所述长轴正交的短轴; （b）通道长度小于10nm; （c）源极掺杂第一极性并具有第一导带; （d）漏极掺杂有与第一极性相反的第二极性，并且漏极具有比第一导带具有更高能量的第二导带。 本文描述了其它实施例。

公开(公告)号：US09304491B2

公开(公告)日：2016-04-05

申请号：US13685401

申请日：2012-11-26

Applicant: Intel Corporation

Inventor： Dmitri E. Nikonov ,  Michael C. Mayberry ,  Vivek K. Singh

IPC: H04N13/04 ,  G03H1/22

CPC classification number: G03H1/2294 ,  G03H2001/2234 ,  G03H2210/30

Abstract: Generally, this disclosure provides systems and methods for generating three dimensional holographic images on a transparent display screen with dynamic image control. The system may include a transparent display screen that includes an array of pixels; a driver circuit configured to control each of the pixels in the array of pixels such that the transparent display screen displays an interference fringe pattern, the interference fringe pattern associated with a hologram; and a coherent light source configured to illuminate the transparent display screen with coherent light, wherein transformation of the coherent light by the interference fringe pattern generates a three dimensional holographic image.

Abstract translation: 通常，本公开提供了用于在具有动态图像控制的透明显示屏上产生三维全息图像的系统和方法。 该系统可以包括包括像素阵列的透明显示屏幕; 驱动器电路，被配置为控制像素阵列中的每个像素，使得透明显示屏幕显示干涉条纹图案，与全息图相关联的干涉条纹图案; 以及被配置为用相干光照亮透明显示屏的相干光源，其中通过干涉条纹图案的相干光的变换产生三维全息图像。

公开(公告)号：US08897047B2

公开(公告)日：2014-11-25

申请号：US13629935

申请日：2012-09-28

Applicant: Intel Corporation

Inventor： George I. Bourianoff ,  Dmitri E. Nikonov

IPC: G11C27/00

CPC classification number: G11C15/02 ,  G11C15/04 ,  G11C15/046

Abstract: An analog associative memory, which includes an array of coupled voltage or current controlled oscillators, matches patterns based on shifting frequencies away from a center frequency of the oscillators. Test and memorized patterns are programmed into the oscillators by varying the voltage or current that controls the oscillators. Matching patterns result in smaller shifts of frequencies and enable synchronization of oscillators. Non-matching patterns result in larger shifts and preclude synchronization of oscillators. The patterns may each include binary data and the pattern matching may be based on discrete shifts. The patterns may each include grayscale data and the pattern matching may be based on continuously-varied shifts. Other embodiments are described herein.

Abstract translation: 包括耦合电压或电流控制振荡器的阵列的模拟相关存储器基于偏离振荡器的中心频率的移位频率匹配模式。 通过改变控制振荡器的电压或电流将测试和存储的模式编程到振荡器中。 匹配模式导致频率偏移较小，并使振荡器能够同步。 非匹配模式导致更大的偏移，并排除振荡器的同步。 这些图案可以各自包括二进制数据，并且模式匹配可以基于离散移位。 这些图案可以各自包括灰度数据，并且图案匹配可以基于连续变化的移动。 本文描述了其它实施例。