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    Open-loop voltage regulation and drift compensation for digitally controlled oscillator (DCO)
    21.
    发明授权
    Open-loop voltage regulation and drift compensation for digitally controlled oscillator (DCO) 有权
    数字控制振荡器（DCO）的开环电压调节和漂移补偿

    公开(公告)号：US09455727B2

    公开(公告)日：2016-09-27

    申请号：US14498728

    申请日：2014-09-26

    Applicant: INTEL CORPORATION

    Inventor： Shenggao Li ,  Guluke Tong ,  Sujatha B. Gowder ,  Fulvio Spagna

    IPC: H03L1/00 ,  H03L7/099 ,  H03L1/02 ,  H03L7/093 ,  H03L7/24

    CPC classification number: H03L7/0991 ,  H03L1/00 ,  H03L1/022 ,  H03L5/00 ,  H03L7/093 ,  H03L7/0995 ,  H03L7/24 ,  H03L2207/06

    Abstract: Embodiments include apparatuses, methods, and systems for open-loop voltage regulation and drift compensation for a digitally controlled oscillator (DCO). in embodiments, a communication circuit may include a DCO, an open-loop voltage regulator, and a calibration circuit. The open-loop voltage regulator may receive a calibration voltage and may generate a regulated voltage. The regulated voltage may be passed to the DCO. During a calibration mode, the calibration circuit may compare the regulated voltage to a reference voltage and adjust the calibration voltage based on the comparison to provide the regulated voltage with a target value. During a monitoring mode, the calibration circuit may receive a tuning code that is used to tune the DCO and further adjust the calibration voltage based on a value of the tuning code.

    Abstract translation: 实施例包括用于数字控制振荡器（DCO）的开环电压调节和漂移补偿的装置，方法和系统。 在实施例中，通信电路可以包括DCO，开环电压调节器和校准电路。 开环稳压器可以接收校准电压并且可以产生调节电压。 调节电压可以传递到DCO。 在校准模式期间，校准电路可以将调节电压与参考电压进行比较，并根据比较调节校准电压，以将调节电压提供给目标值。 在监视模式期间，校准电路可以接收用于调谐DCO的调谐码，并且基于调谐码的值进一步调整校准电压。

    High performance interconnect physical layer
    22.
    发明授权
    High performance interconnect physical layer 有权
    高性能互连物理层

    公开(公告)号：US09208121B2

    公开(公告)日：2015-12-08

    申请号：US14538937

    申请日：2014-11-12

    Applicant: INTEL CORPORATION

    Inventor： Venkatraman Iyer ,  Darren S. Jue ,  Robert G. Blankenship ,  Fulvio Spagna ,  Debendra Das Sharma ,  Jeffrey C. Swanson

    IPC: G06F13/42 ,  G06N99/00

    CPC classification number: G06F13/4291 ,  G06F1/24 ,  G06F1/3287 ,  G06F13/1678 ,  G06F13/42 ,  G06F13/4282 ,  G06N99/005

    Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.

    Abstract translation: 周期性控制窗口嵌入在要通过串行数据链路发送的链路层数据流中，其中控制窗口被配置为提供物理层信息，包括用于启动数据链路上的状态转换的信息。 可以在数据链路的链路发送状态期间发送链路层数据，并且控制窗口可以中断发送猝发。 在一个方面，信息包括指示改变链路上的活动车道数目的尝试的链路宽度转换数据。

    HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER
    23.
    发明申请
    HIGH PERFORMANCE INTERCONNECT PHYSICAL LAYER 审中-公开
    高性能互连物理层

    公开(公告)号：US20150067208A1

    公开(公告)日：2015-03-05

    申请号：US14538937

    申请日：2014-11-12

    Applicant: INTEL CORPORATION

    Inventor： Venkatraman Iyer ,  Darren S. Jue ,  Robert G. Blankenship ,  Fulvio Spagna ,  Debendra DAS Sharma ,  Jeffrey C, Swanson

    IPC: G06F13/42 ,  G06N99/00

    CPC classification number: G06F13/4291 ,  G06F1/24 ,  G06F1/3287 ,  G06F13/1678 ,  G06F13/42 ,  G06F13/4282 ,  G06N99/005

    Abstract: A periodic control window is embedded in a link layer data stream to be sent over a serial data link, where the control window is configured to provide physical layer information including information for use in initiating state transitions on the data link. The link layer data can be sent during a link transmitting state of the data link and the control window can interrupt the sending of flits. In one aspect, the information includes link width transition data indicating an attempt to change the number of active lanes on the link.

    Abstract translation: 周期性控制窗口嵌入在要通过串行数据链路发送的链路层数据流中，其中控制窗口被配置为提供物理层信息，包括用于启动数据链路上的状态转换的信息。 可以在数据链路的链路发送状态期间发送链路层数据，并且控制窗口可以中断发送猝发。 在一个方面，信息包括指示改变链路上的活动车道数目的尝试的链路宽度转换数据。

    Programmable clock data recovery (CDR) system including multiple phase error control paths
    26.
    发明授权
    Programmable clock data recovery (CDR) system including multiple phase error control paths 有权

    公开(公告)号：US10523411B2

    公开(公告)日：2019-12-31

    申请号：US15939795

    申请日：2018-03-29

    Applicant: Intel Corporation

    Inventor： Shenggao Li ,  Ji Chen ,  Michael De Vita ,  Fulvio Spagna ,  Guluke Tong

    IPC: H04L7/033 ,  G06F13/40 ,  G06F13/42 ,  H03L7/089 ,  H03L7/091

    Abstract: Some embodiments include apparatus having sampling circuitry, a first circuit path, a second circuit path, and a digitally controlled oscillator (DCO). The sampling circuit samples an input signal and provide data information and phase error information based on the input signal. A first circuit path provides proportional control information based on the data information and phase error information. A second circuit path provides integral control information based on the data information and phase error information. The first circuit path operates at a frequency higher than the second circuit path. The DCO generates a clock signal and controls the timing of the clock signal based on the integral control information and the proportional control information.

    PHY RECALIBRATION USING A MESSAGE BUS INTERFACE
    27.
    发明申请
    PHY RECALIBRATION USING A MESSAGE BUS INTERFACE 审中-公开

    公开(公告)号：US20190303342A1

    公开(公告)日：2019-10-03

    申请号：US16446470

    申请日：2019-06-19

    Applicant: Intel Corporation

    Inventor： Michelle C. Jen ,  Minxi Gao ,  Debendra Das Sharma ,  Fulvio Spagna ,  Bruce A. Tennant ,  Noam Dolev Geldbard

    IPC: G06F13/42

    Abstract: An interface couples a controller to a physical layer (PHY) block, where the interface includes a set of data pins comprising transmit data pins to send data to the PHY block and receive data pins to receive data from the PHY block. The interface further includes a particular set of pins to implement a message bus interface, where the controller is to send a write command to the PHY block over the message bus interface to write a value to at least one particular bit of a PHY message bus register, bits of the PHY message bus register are mapped to a set of control and status signals, and the particular bit is mapped to a recalibration request signal to request that the PHY block perform a recalibration.

    Phase frequency detector
    28.
    发明授权
    Phase frequency detector 有权

    公开(公告)号：US10374616B2

    公开(公告)日：2019-08-06

    申请号：US15991584

    申请日：2018-05-29

    Applicant: Intel Corporation

    Inventor： Wenyan Vivian Jia ,  Shenggao Li ,  Fulvio Spagna

    IPC: H03L7/087 ,  H03D13/00 ,  G04F10/00

    Abstract: Described is an apparatus comprising: a first phase frequency detector (PFD) to determine a coarse phase difference between a first clock signal and a second clock signal, the first PFD to generate a first output indicating the coarse phase difference; and a second PFD, coupled to the first PFD, to determine a fine phase difference between the first clock signal and the second clock signal, the second PFD to generate a second output indicating the fine phase difference.

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