公开(公告)号：US20240114693A1

公开(公告)日：2024-04-04

申请号：US17958202

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Christopher M. Neumann ,  Brian Doyle ,  Nazila Haratipour ,  Shriram Shivaraman ,  Sou-Chi Chang ,  Uygar E. Avci ,  Eungnak Han ,  Manish Chandhok ,  Nafees Aminul Kabir ,  Gurpreet Singh

IPC: H01L27/11514 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11504

CPC classification number: H01L27/11514 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11504

Abstract: In one embodiment, an apparatus includes a first metal layer, a second metal layer above the first metal layer, a first metal via generally perpendicular with and connected to the first metal layer, a second metal via generally perpendicular with and connected to the second metal layer, a third metal via generally perpendicular with and extending through the first metal layer and the second metal layer, a ferroelectric material between the third metal via and the first metal layer and between the third metal via and the second metal layer, and a hard mask material around a portion of the first metal via above the first metal layer and the second metal layer, around a portion of the second metal via above the first metal layer and the second metal layer, and around a portion of the ferroelectric material above the first metal layer and the second metal layer.

公开(公告)号：US11837644B2

公开(公告)日：2023-12-05

申请号：US16579069

申请日：2019-09-23

Applicant: Intel Corporation

Inventor： Rami Hourani ,  Richard Vreeland ,  Giselle Elbaz ,  Manish Chandhok ,  Richard E. Schenker ,  Gurpreet Singh ,  Florian Gstrein ,  Nafees Kabir ,  Tristan A. Tronic ,  Eungnak Han

IPC: H01L29/423 ,  H01L29/78 ,  H01L23/522 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/4238 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L23/5226 ,  H01L27/0886 ,  H01L29/41775 ,  H01L29/7851

Abstract: Contact over active gate structures with metal oxide cap structures are described. In an example, an integrated circuit structure includes a plurality of gate structures above substrate, each of the gate structures including a gate insulating layer thereon. A plurality of conductive trench contact structures is alternating with the plurality of gate structures, each of the conductive trench contact structures including a metal oxide cap structure thereon. An interlayer dielectric material is over the plurality of gate structures and over the plurality of conductive trench contact structures. An opening is in the interlayer dielectric material and in a gate insulating layer of a corresponding one of the plurality of gate structures. A conductive via is in the opening, the conductive via in direct contact with the corresponding one of the plurality of gate structures, and the conductive via on a portion of one or more of the metal oxide cap structures.

公开(公告)号：US11545449B2

公开(公告)日：2023-01-03

申请号：US16017409

申请日：2018-06-25

Applicant: INTEL CORPORATION

Inventor： Paul A. Nyhus ,  Gurpreet Singh

IPC: H01L23/58 ,  H01L23/00 ,  H01L29/34 ,  H01L21/768 ,  H01L23/31

Abstract: A guard ring structure includes a plurality of first groups of concentric guard rings encompassing an active region of an integrated circuit, the concentric guard rings of the first groups having a guard ring pitch of less than 80 nm. The concentric guard rings of the first groups have a single, closed path that is distinct from an adjacent guard ring and defines a rectangular geometry with rounded corners. Second groups of guard rings are interspersed with and concentrically arranged with the first groups, where each corner region of the second groups include at least one guard ring defect. A method of fabricating a guard ring structure for an integrated circuit is also disclosed.

公开(公告)号：US20220199462A1

公开(公告)日：2022-06-23

申请号：US17511693

申请日：2021-10-27

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Florian Gstrein ,  Eungnak Han ,  Marie Krysak ,  Tayseer Mahdi ,  Xuanxuan Chen ,  Brandon Jay Holybee

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: Methods for forming via openings by using a lamellar triblock copolymer, a polymer nanocomposite, and a mixed epitaxy approach are disclosed. An example method includes forming a guiding pattern (e.g., a topographical guiding pattern, chemical guiding pattern, or mixed guiding pattern) on a surface of a layer of an IC device, forming lamellar structures based on the guiding pattern by using the lamellar triblock copolymer or forming cylindrical structures based on the guiding pattern by using the polymer nanocomposite, and forming via openings by removing a lamella from each of at least some of the lamellar structures or removing a nanoparticle from each of at least some of the cylindrical structures.

公开(公告)号：US20220173034A1

公开(公告)日：2022-06-02

申请号：US17671543

申请日：2022-02-14

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Leonard Guler ,  Paul Nyhus ,  Gobind Bisht ,  Jonathan Laib ,  David Shykind ,  Gurpreet Singh ,  Eungnak Han ,  Noriyuki Sato ,  Charles Wallace ,  Jinnie Aloysius

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423

Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

公开(公告)号：US20210074632A1

公开(公告)日：2021-03-11

申请号：US16562346

申请日：2019-09-05

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Leonard Guler ,  Paul Nyhus ,  Gobind Bisht ,  Jonathan Laib ,  David Shykind ,  Gurpreet Singh ,  Eungnak Han ,  Noriyuki Sato ,  Charles Wallace ,  Jinnie Aloysius

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L29/423 ,  H01L29/417

Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

公开(公告)号：US10886175B2

公开(公告)日：2021-01-05

申请号：US16347507

申请日：2016-12-23

Applicant: Intel Corporation

Inventor： Eungnak Han ,  Rami Hourani ,  Florian Gstrein ,  Gurpreet Singh ,  Scott B. Clendenning ,  Kevin L. Lin ,  Manish Chandhok

IPC: H01L29/06 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L23/522

Abstract: Selective hardmask-based approaches for conductive via fabrication are described. In an example, an integrated circuit structure includes a plurality of conductive lines in an inter-layer dielectric (ILD) layer above a substrate. The plurality of conductive lines includes alternating non-recessed conductive lines and recessed conductive lines. The non-recessed conductive lines are substantially co-planar with the ILD layer, and the recessed conductive lines are recessed relative to an uppermost surface of the ILD layer. A dielectric capping layer is in recess regions above the recessed conductive lines. A hardmask layer is over the non-recessed conductive lines but not over the dielectric capping layer of the recessed conductive lines. The hardmask layer differs in composition from the dielectric capping layer. A conductive via is in an opening in the dielectric capping layer and on one of the recessed conductive lines. A portion of the conductive via is on a portion of the hardmask layer.

公开(公告)号：US12266527B1

公开(公告)日：2025-04-01

申请号：US17559406

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Gurpreet Singh ,  Nityan Labros Nair ,  Nafees A. Kabir ,  Eungnak Han ,  Xuanxuan Chen ,  Brandon Jay Holybee ,  Charles Henry Wallace ,  Paul A. Nyhus ,  Manish Chandhok ,  Florian Gstrein ,  David Nathan Shykind ,  Thomas Christopher Hoff

IPC: H01L21/027

Abstract: Described herein are IC devices include patterned conductive layers, such as metal gratings and gate layers, and patterned layers formed over the patterned conductive layers using a directed self-assembly (DSA)-enabled process with DSA assisting features. A patterned conductive layer may have non-uniform features, such as large regions of insulator within a metal grating, or varying gate lengths across a gate layer. The DSA assisting features enable the formation of patterned layers, e.g., layers with different hard mask materials replicating the structure of the conductive layer below, even over non-uniform features.

公开(公告)号：US12131991B2

公开(公告)日：2024-10-29

申请号：US17671543

申请日：2022-02-14

Applicant: Intel Corporation

Inventor： Manish Chandhok ,  Leonard Guler ,  Paul Nyhus ,  Gobind Bisht ,  Jonathan Laib ,  David Shykind ,  Gurpreet Singh ,  Eungnak Han ,  Noriyuki Sato ,  Charles Wallace ,  Jinnie Aloysius

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/423

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/5283 ,  H01L29/41725 ,  H01L29/4232

Abstract: An integrated circuit interconnect structure includes a first metallization level including a first metal line having a first sidewall and a second sidewall extending a length in a first direction. A second metal line is adjacent to the first metal line and a dielectric is between the first metal line and the second metal line. A second metallization level is above the first metallization level where the second metallization level includes a third metal line extending a length in a second direction orthogonal to the first direction. The third metal line extends over the first metal line and the second metal line but not beyond the first sidewall. A conductive via is between the first metal line and the third metal line where the conductive via does not extend beyond the first sidewall or beyond the second sidewall.

公开(公告)号：US12012473B2

公开(公告)日：2024-06-18

申请号：US17032517

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： James Munro Blackwell ,  Robert L. Bristol ,  Xuanxuan Chen ,  Lauren Elizabeth Doyle ,  Florian Gstrein ,  Eungnak Han ,  Brandon Jay Holybee ,  Marie Krysak ,  Tayseer Mahdi ,  Richard E. Schenker ,  Gurpreet Singh ,  Emily Susan Walker

IPC: G03F7/11 ,  C08F265/02 ,  C08F265/04 ,  H01L23/522 ,  H01L23/528

CPC classification number: C08F265/04 ,  C08F265/02 ,  G03F7/11 ,  H01L23/5226 ,  H01L23/528

Abstract: Disclosed herein are structures and techniques utilizing directed self-assembly for microelectronic device fabrication. For example, a microelectronic structure may include a patterned region including a first conductive line and a second conductive line, wherein the second conductive line is adjacent to the first conductive line; and an unordered region having an unordered lamellar pattern, wherein the unordered region is coplanar with the patterned region.